FPGA Implementation of Image De-noising using Haar Wavelet Transform

FPGA Implementation of Image De-noising using Haar Wavelet Transform

Ramesha K. P

1. Student,

   VLSI & Embedded Systems, VTU Extn. Centre,

   UTL Technologies Ltd., Bangalore, India

   Ramanareddy K. V Assistant Professor, VTU Extn. Centre, UTL Technologies Ltd., Bangalore, India

   Dr. Siva Yellampalli Prof & Principal, VTU Extn. Centre,

   UTL Technologies Ltd., Bangalore, India

   Abstract: Noise components are added into image due to various reasons like camera problem, communication channel error etc. To eliminate this noise problem various noise filtering methods are introduced. But the performance of those filters is not good and produces large latency. In this paper we propose FPGA implementation of image de-noising using Haar wavelet transform. Haar wavelet transform is applied on noisy image to generate all four bands and threshold is applied on it to remove noise. Then inverse transform is used to generate de-noised image. The proposed architecture improves performance parameters with respect to existing techniques in terms of both software and hardware

   Keywords Image De-noising, Discrete Wavelet Transform, Thresholding and FPGA Implementation

   1. INTRODUCTION

      Image more or less degraded by noise in transmission stage to and from the storage media. The image may also distort because of inherent characteristics of noisy channels and degradation of equipment in the measurement process. Different types of noise appeared in the image such as white noise, shot noise, salt & pepper noise, Gaussian noise and speckle noise. The de-noising suppress the additive noise preventing the important signal features of the image. Many noise reduction techniques developed so far use the filtering process for removing the noise in the distorted image. The image de-noising objective is obtain best approximation of original image from the distorted image preserving the important features of image. This can be achieved by wavelet transform. The quality of image can be measured in terms of PSNR [1]. In this project DWT is used to obtain the coefficients of the test images for removing noise without altering edges, corners and other sharp structures of the image. The major problem with the de-noising methods based on hard and soft thresholding is that the selection of threshold value [2] for image de-noising. The selection of threshold depends on the noise variance, size of the image, the scale parameter and number of decomposition [3].

      Wavelet transform is used in signal and image processing for its localization property. Wavelet threshold is a method that uses wavelet transform for de-noising of image by killing the co-efficient which are insignificant to some threshold value. The sub band co-efficient of the discrete wavelet are modeled as identically independent noise distributed randomly called Gaussian distribution [4]. The de- noised co-efficients are evaluated by MSE. Some of the de-

      noising algorithms based on the shrinkage of wavelet co- efficients are affected by Gaussian noise retaining only large co-efficients and setting the rest to zero. Shrinkage depends on the energy of neighboring pixel whereas wavelet shrinkage based method uses the energy of neighboring pixels to improve the performance of de-noising in terms of PSNR compared to other thresholding technique.

      Wavelets are the newly developed signal and image processing tool used in the analysis of various time scales of local properties of complex signals. These features of wavelet transform finds applications in various fields such as astrophysics, telecommunication, video coding and imagery and geophysics. Wavelets are the basis for the new techniques for the analysis and synthesis of the signal in image compression and de-noising.

      Most of the algorithms are highly computational demanding large amount of time to produce a restored image, when implemented in software on a general purpose CPU. This motivates the implementation of specialized hardware to deal with a corrupted image, producing the restored image in the fastest time possible and with enhanced quality.

   2. LITERATURE SURVEY

      V Tataru [1] presents improved noise suppression technique with Haar wavelet transform.The Haar transform produces both average and difference values of neighbouring co- efficients after the application of Haar transform over the corrupted image. So Haar transform produces positive and negative values depends on variation of random variables because of noise. The results shows proposed modified Neigh shrink method performs better than other methods in Wavelet transform is used in signal and terms of PSNR and MSE.

      M.Neelima and M pasha [2] present a wavelet based noise elimination scheme over image using threshold technique. The proposed Neigh Shrink method is based on decimated wavelet transform uses the universal threshold and size of the neighbouring window. The bottleneck of the proposed method is it uses the same universal threshold and window size remains constant. The results show the proposed neigh shrink method performs better than other methods in terms of PSNR and MSE.

      Akhilesh et al., [3] presents different threshold estimation approach for wavelet based image de-noising. The adaptive threshold depends on scale, number of decomposition and noise variance. The proposed semi soft threshold based on

      sub band, recovers the image from noisy image. The results show the proposed method performs better than other methods in terms of PSNR and MSE.

      Pankaj Hedaoo and Swati [4] present various wavelet based adaptive thresholding approaches for image de-noising. This method uses wavelet threshold for removing white Gaussian noise by statistical modelling of wavelet coefficients and the optimal choice of threshold. The proposed Bayes Shrink perfoms better than Sure Shrink and visualization shrink methods in terms of PSNR and MSE.

      Karthik V Hegde et al., [5] presents an adaptive reconfigurable architecture for image denoising this architecture detects the noise dynamically, so better image denoising can be achieved. This architecture detects Gaussian and impulse noise using separate hardware detection unit and noise can be removed by using filters. This architecture also contains decision making unit to detect the presence of noise and type of noise. The proposed architecture is implemented on Xilinx virtex-6 FPGA kit. The proposed architecture provides better performance compared to the standard filters utilizing the smaller area and less hardware resources under various noise conditions.

      Basheer and Mohammed [6] present FPGA implementation of two dimensional discrete wavelet transform architecture for image de-noising. This design removes salt & pepper and Gaussian noise from corrupted grey scale images. The simple hard thresholding approach is utilized to remove the noise based on universal threshold. The proposed architecture is developed on the 5/3 DWT lifting scheme of wavelet filter. This technique uses processor unit, control unit and on chip and off chip memory for speed up of operation. This architecture is developed and synthesized using VHDL and implemented over FPGA for checking the results. This architecture based on lifting scheme uses the simple arithmetic computation, easy hardware implementation, fast and easy hardware implementation.

      Ashok and Anu [7] presents FPGA implementation of adaptive wavelet threshold based image de-noising. This paper proposes various thresholding techniques such as neigh shrink, Bayes shrink and Visu shrink to remove noise from the corrupted noisy image. These techniques canot recover original noise free image since the threshold value does not

      Srinivasarao and Indrajit [9] present a parallel lifting based architecture of three dimensional architecture of 3D DWT. The parallel lifting scheme has the advantage of high throughput and efficient memory architecture. The 3D DWT is constructed by spatial and temporal processors. The higher throughput of this architecture reduces the computation of the frame and consumes less power and low latency. The proposed architecture is synthesized using verilog and 90nm CMOS technology. This architecture has been synthesized for Xilinx and FPGA.

      Yamuna and Chandrashekar [10] present modified lifting scheme DWT architecture for image compression. This architecture uses the interfaces for the data processing operations. The design is implemented using Verilog hardware description language VHDL and synthesized using Spartan FPGA kit. The performance of proposed scheme is better than the other in terms of frequency and power consumption.

   3. PROPOSED ARCHITECTURE

      The block diagram of proposed architecture is shown in Fig.1. First different sizes of images are converted into uniform size 256×256 and 2D Haar wavelet transform is applied on the noisy input image to generate all four co- efficients (i.e. LL, LH, HL and HH). Threshold is applied on LH, HL and HH band to remove negative numbers which are generated by noisy components. By using IDWT we reconstruct the image where noise components are less which is justified by calculating PSNR value.

      Fig.1: Block Diagram of Proposed Image De-noising Architecture

      3.1. Discrete Wavelet Transform

      Basic Haar Wavelet is used to generate all four sub-band coefficients as LL, LH, HL and HH. The equations for 2×2 1D Haar wavelet is given in equation (1) and (2) which generate L and H bands

      minimize the noisy co-efficients across scales. The proposed

      de-noising method adaptively set the threshold by shrinking

      = +

      2

      (1)

      the wavelet co-efficients. The proposed architecture uses DWT decomposition developed by VHDL and realised over FPGA kit. The proposed architecture reduces the processing

      =

      2

      2

      Where, A

      (2)

      and B are the pixel data from image.

      time, high throughput rate, simple computations and occupies less memory space compared to other architecture.

      Chin-Fa Hsieh et al., [8] presents hardware architecture of one dimensional DWT for reduction of noise. This paper proposes forward and inverse DWT operations and implemented by the folded transformation. The pipelined scheme was introduced to speed up the clock and is scalable for different levels of resolution. The lifting scheme uses the shift operations and designed by adders independent of the resolution levels. The architecture developed by Verilog hardware description hardware description language VHDL and results are verified on Quartos-II and implemented on FPGA.

      The basic block diagram of forward and inverse 2D-DWT

      wavelet transform is shown in Fig.2

      Fig. 2: Forward and Inverse 2D-DWT

      The Haar wavelet decomposition and reconstruction of Lena image is shown in Fig.3.

      Fig. 3: The Decomposition and Reconstruction of Lena Image

      3.2 Threshold

      Threshold block is used to remove negative values generated by noise components in image (i.e. LH, HL and HH). These negative values only shift the intensity value of a image but does not carry any information related to image. So, the threshold block check the co-efficients of DWT block and if any negative value comes then it blocks the value by sending zero. The equation of threshold block is given in equation (3)

      (b)

      = {

      = {

      0;

      ;

      (3).

   4. SIMULATION RESULTS AND PERFORMANCE ANALYSIS

      In this section the proposed design is simulated using MATLAB R2012a (7.14.0.739) version.

      4.1. Performance Parameters

      In this section, the performance parameters are evaluated using PSNR values between original noiseless image and de- noised image by using the formula (4) as

      10

      10

      = 10 log 2552 (4)

      Where, MSE = 1 1 1[IN(i, j) OP(i, j)]2

      (c)

      Fig.5: (a) Original image, (b) Noisy image and (c) De-noised Image by proposed Method

      4.3. Performance Analysis

      To analyze the performance of proposed architecture we take different test images and encrypt same information into the image and check PSNR values using equation (4). Those values are tabulated into Table 1.

      Image	PSNR(dB)
      Lena	36.46
      Cameraman	35.96
      Peppers	38.1
      Goldhill	39.34

      Image	PSNR(dB)
      Lena	36.46
      Cameraman	35.96
      Peppers	38.1
      Goldhill	39.34

      TABLE 1: PSNR Values for different input images

      =0

      =0

      IN(i,j) is input (Noisy) image pixel values. OP(i,j) is ouput (De-noised) image pixel values. AB is the image dimensions (256×256).

      4.2. Image Output

      The original, noisy and de-noised image is shown in Fig.5 where de-noising is done by proposed technique.

      (a)

   5. PERFORMANCE COMPARISONS WITH EXISTING TECHNIQUES

      The performance comparisons of existing technique with proposed technique are discussed in this section in terms of PSNR values.

      1. PSNR Comparisons

         Table 2 shows the PSNR values of proposed and the existing techniques. The proposed technique is compared with existing techniques presented by Naseer and Mustafa [6] and Ashok and Anu [7]. It is observed that the PSNR values of proposed algorithm are higher compared to existing algorithms.

         TABLE 2: Comparison of PSNR values of Proposed Method with the Existing Methods.

         Image	Naseer and Mustafa [6]	Ashok and Anu [7]	PSNR (dB)
         Cameraman	18.04	—	35.96
         Lena	17.88	34.874	36.46
         Peppers	13.98	—	38.1
         Goldhill	18.25	—	39.34

      2. Hardware Comparisons

      Table 3 shows the comparison of hardware utilization of proposed de-noising technique with the existing technique proposed by Naseer and Mustafa [6]. It is observe that the proposed algorithm uses lesser hardware resources due to simple architecture.

      TABLE 3: Comparison of PSNR values of Proposed Method with the Existing Methods.

      Parameters	Naseer and Mustafa [6]	Proposed
      No. of Slices	1464	725
      No.of Slice Flip- flops	818	27
      No. of Four input LUTs	2321	1655
      Maximum Frequency (MHz)	52.84	206.605

   6. CONCLUSION

In this paper we proposed FPGA architecture for image de- noising using Haar wavelet transform. The proposed architecture can be able to de-noise image better than existing techniques. This is because most of noise components produce negative value in LH, HL and HH band which is then removed by threshold by making those values to zero. But the total system uses large amounts of external memory for storing the imagewhich is drawback of this architecture.

REFERENCES

1. Vasilica Tataru, Improved Image De Noising in Haar Wavelet Domain Using Neighboring Coefficients, International Journal of Computer Science and Network Security, Vol. 11 No.2, February 2011.

2. M.Neelima and Md. Mahaboob Pasha, Wavelet Transform Based On Image Denoising using Thresholding Techniques, International Journal of Advanced Research in Computer and Communication Engineering, Vol. 3, Issue 9, September 2014.

3. Akhilesh Bijalwan, Aditya Goyal and Nidhi Sethi, Wavelet Transform Based Image Denoising using Threshold Approaches, International Journal of Engineering and Advanced Technology, Vol.1, Issue. 5, pp. 218-221, June 2012.

4. Pankaj Hedaoo and Swati S Godbole, Wavelet Thresholding Approaches for Image Denoising, International Journal of Network Security and its Applications, Vol. 3, No. 4, pp. 16-21, July 2011.

5. Kartik V Hegde, Vadiraj Kulkarni, Harshavardhan R, and Sumam David S, Adaptive Reconfigurable Architecture for Image Denoising, IEEE International Parallel and Distributed Processing Symposium Workshops, 2015.

6. Naseer M. Basheer and Mustafa Mushtak Mohammed, Image Denoising using FPGA Based 2D-DWT Architecture ,International Journal of Recent Technology and Engineering, Vol. 2, Issue. 4, pp. 92- 97, September 2013.

7. Chipy Ashok and Anu V.S., FPGA Implementation of Image Denoising using Adaptive Wavelet Thresholding, International Journal of Advanced Research in Computer and Communication Engineering, Vol. 4, Issue. 7, pp. 288-292, July 2015.

8. Chin-Fa Hsieh, Tsung-Han Tsai, Chih-Hung Lai and Shu-Chung Yi, An Efficient Architecture for 1D Discrete Wavelet Transform for Noise Reduction, International Journal of Advancements in Computing Technology, Vol. 5, No. 3, pp. 412-419, February 2013.

9. B.K.N. Srinavasarao and Indrajit Chakrabarti, High Speed VLSI Architecture for 3-D Discrete Wavelet Transform, Cornell University Library, pp. 1-13, September 2015.

10. K. Yamuna and C. Chandrasekhar, Design and Implementation of Efficient Lifting Based DWT Architecture using Wallace Tree Multiplier for Compression, International Journal of Engineering Research and Applications, Vol. 3, Issue. 4, pp. 1772-1777, 2013.