Hysteresis Current Control of Split Capacitor type Elementary Additional Series Positive Output SLC

Hysteresis Current Control of Split Capacitor type Elementary Additional Series Positive Output SLC

Abstract

Super lift converter (SLC) is a new series of DC/DC converter possessing high voltage transfer gain, high efficiency, reduced ripple voltage and current. Super lift technique armed by split capacitors increases the output voltage in higher geometric progression. This paper focuses on splitting the input side capacitor of the additional series positive output super lift converter response controlled with two different control techniques. The first control technique is PI control, while the second control technique is sliding mode control. The sliding mode control shows to be more effective than PI control especially when dynamic tests are applied. Sliding Mode control designed to regulate the converter against audio susceptibility and output impedance variation. Simulation study of the proposed converter along with the controller has been carried out in MATLAB/SIMULINK to investigate the static and dynamic response of the converter.

1. Introduction

   Super lift converter for a given input voltage, the output voltage increases stage by stage in geometric progression. Voltage conversion from line side to load side voltage. Positive Output Super Lift Converter (POSLC) is a new series of DC to DC converter possessing high voltage transfer gain, high power density, high efficiency, reduced ripple voltage and current. It effectively increases the voltage transfer gain in higher proportion [1-4]. Split capacitor type positive output super lift converter splits the energy storage element capacitor into parts, effectively increases the energy storage in each capacitor. The stored energy in the inductor and capacitor is pumped to the load.

   Split stage in POSLC converter is defined as stage, if = 2 the capacitor in the circuit topology is

   splitted into two capacitor in the circuit which is charged to the supply voltage when the switch is in the ON condition. Positive output super lift converter is classified into two series namely main series and additional Series, these two series differs from the number of energy storage elements used in their topology.

   Proportional Integral (PI) controller has been implemented for the proposed DC-DC converter. For same proposed DC-DC converter with sliding mode control (SMC) was designed. In both models converter was tested in steady state and under different disturbances. Both models showed acceptable results. This paper considers the output voltage and inductor current of the Buck converter controlled with two different control techniques, PI control and SMC. The results of both models are compared in steady state, transient region, and under line and load variations.

   In this paper, state-space averaged model for split type elementary additional series positive output super lift Luo converter (SEPOSLLC) has been derived.

2. Converter Operation and Modeling of Split Type Positive Output Super Lift Converter

   1. Circuit Description and Operation

      The circuit diagram of the Split Capacitor type positive output super lift converter is shown in Figure 1. It includes DC supply voltage Vin, capacitors C1 to C3, C11, C12 inductor L, power switch (n-channel MOSFET) S, freewheeling diodes D1 to D7, D11 and D12 and load resistance R.

      In the description of the converter operation, it is assumed that all the components are ideal and also split capacitor type elementary additional series

      = Vin kT = Vo – V1 – Vin (1- k)T

      iL L L

      (1)

      V = 1

      + 3 – 2k V

      (2)

      0 1- k 1- k in

      The voltage transfer gain is

      Figure 1. split capacitor type elementary additional series positive output super lift

      G = VO =

      Vin

      1 + 3 – 2k

      1- k 1- k

      (3)

      converter

      positive output super lift converter operates in a continuous conduction mode. Figure 2 and 3 show the modes of operation of the converter. The voltage across the capacitors C1 and C2 are charged to Vin during the on state of the switch under the steady state condition.

      The input current iin is equal to ( iL + iC1 + iC2 ) during switching-on and only equal to iL during switching-off. Capacitor current iC1 and iC2 is equal to iC3 during switching-off. In steady state, the Voltage across the capacitor C1, C2 is equal to Vin. The following relations are obtained [8].

      iin – off

      = iL – off

      = iC1 – off + iC11 – off

      iin – on = iL – on + iC1 – on + iC2 – on

      (4)

      I

      O

      iC1 – on = k

      If inductance L1 is large enough, iL is nearly equal to its average current IL. Therefore

      Figure 2. Mode 1 operation

      iin – off

      = IL = iC1 – off + iC11 – off

      The current iL flowing through inductor L increases

      iC1 – off = iC2 – off

      = iC3 – off

      with voltage Vin during switching-on period kT

      iin – off = IL =

      i = i

      2IO (1-k)

      IO

      =

      (5)

      C1 – off C2 – off

      And average input current

      (1-k)

      Iin = kiin-on + (1- k)iin-off =

      4Io

      (1 k)

      (6)

      L

      The variation ratio of inductor current iL is

      Figure 3. Mode 2 operation

      = i / 2 = iL

      k (1-k )2R 8 (4-2k ) L1f

      (7)

      Inductor L decreases with voltage

      [VO V1- Vin] during switching-off period (1 k)T . The inductor current increases during switch S on,

      The ripple voltage of output Vo is

      V = Q = (1- k )T Io = (1- k )Vo

      (8)

      and decreases during switch S off. The peak to peak

      o C2 C2

      fC2 R

      current ripple in the inductor is the same during steady state operation and it is given as

      Therefore, the variation ratio of output voltage Vo is

      = Vo / 2 = ( 1- k )

      (9)

      E = 1 / (C2 + C4 * (3 – 2k / 1- k))

      Vo 2RfC2

      F = (C1 * C) / (C3 * C1 + C4 * C3 * C) (12)

   2. State space modeling

      . . . . . .

      State variables X1 , X2 , X3 , X4 , X5 , X6 are chosen as the current iL1, the voltage VC1, VC2, VC3, VC11,VC12 respectively. From Figure 2 When the switch is closed, the state space equation is given as

      X 1 = U1

      L

      By using state space averaging method [7], the state space averaged equation in matrix form of the split capacitor type elementary additional series positive output super lift converter is given as

      0	0	0	0	0	0
      -k + D(1- k) + C2	0	0	0	0	0
      -k + E(1- k) + C2	0	0	0	0	0
      Bk + F(1- k) + C2	0	0	0	0	0
      Ck + C1(1- k) 0 0 0 0 0 + C

      2k L

      X 2 = U1 – X1

      Rin(C1 + C2) (C1 + C2)

      U

      X 1 C1

      X 2

      X1 k Rin(C1 + C2)

      X2

      X 3 =/p>

      1 – X1

      (10) C k

      1

      Rin(C1 + C2) (C1 + C2)

      A * U

      X 3 = –

      * X3 +

      Rin(C1 + C2)

      * U1

      X 4 =

      1 – X1

      X 4 C

      X4 Bk

      Rin(C1 + C2) (C1 + C2)

      1

      X 5 –

      X5 Rin(C1 + C2)

      X 5 =

      B * U1

      – X1

      X 6 C

      X6 Ck

      Rin(C1 + C2) (C1 + C2)

      1 2

      X 6 = –

      X6 RC5

      C1C4(1- k) C5

      0 0 0 0

      -1

      RC5

      Rin(C1 + C2) 0

      In Figure 3 when the switch is open, the state space equation of split capacitor type elementary additional series positive output super lift converter is given as

      V = AV + BU (13)

      Its output equation is given as

      V0 = VC12 (14)

      Where Rin is internal resistance of source, u is input variable, k is duty cycle or the status of the

      X 1 =

      X 2 =

      X 3 =

      k * U1 (1- k) * L

      X1

      D * (C1 + C4) X1

      D * (C1 + C4)

      (11)

      switches, X1, X2, X3, X4, X5 and X6 are the vectors of the state variables ( iL1, VC1, VC2, VC3, VC11, VC12 ) and their derivatives respectively.

3. Design of PI Control

   The PI control is designed to ensure the specified

   desired nominal operating point, to regulate the voltage for split capacitor type elementary additional

   X 4 = E * X1

   X 5 = F * X1

   series positive output super lift converter. The PI control settings proportional gain (KP) and integral

   X 6 = –

   X6

   RC5

   time (Ti) are designed using Zeigler Nichols tuning method. Values of L and T obtained from open loop of split capacitor for enhanced positive output super lift luo converter are as follows L = 0.0002s and time constant T = 0.004s. The delay

   Where the A, B, D, E, F are constants. They are

   given below

   A = B = (3 – 2k / 1- k) * (C4 / C3) C = (3 – 2k / 1- k)

   D = 1 / (C1 + C4 * (3 – 2k / 1- k))

   time and time constant are determined by drawing a tangent line at the inflection point of the S-shaped curve and determining the intersections of the tangent line with the time axis and line output [10]. Ziegler and Nichols suggested to set the values of KP= 1.8 and Ti = 0.0066 s [6].

   SEPOSLC

   Figure 4. S- Shaped curve of open loop response of SEPOSLC

   Figure 5. Simulink simulation model of PI control

   The PI control optimal setting values (Kp and Ti) are obtained by finding the minimum values of integral of square of error (ISE), integral of time of square of error (ITAE) and integral of absolute of error (IAE), which is listed in Table 1.

   Table 1.Simulated Results Of Minimum Values Of Ise, Iae, Itae And Optimal Setting Values Of Kp And Ti

   ISE	IAE	ITAE	Kp	Ti (s)
   0.00154	0.0154	0.3059	0.01205	0.0133

   Figure 6. Simulation model of PI control with split capacitor type elementary additional series positive output super lift converter

4. Design of Sliding Mode Control

   SMC is a non-linear control which complies with the non-linear structure of switch mode power supply. The control topology consists of a linear and non-linear part. The non-linear parameter can be selected, while it is left to the designer to tune the linear part and get the optimum values depending on the application. Figure 6 shows the control structure of SMC. It consists of two control loops, the output voltage is subtracted from the reference voltage and the difference is passed through an integral action. The output of the integral is amplified through a gain and the result is subtracted from the inductor loop, the difference is passed through a hysteresis. One major drawback of this model is the lack of a standard procedure to select the gain. The hysteresis parameter can be selected by measuring the peak-to- peak inductor current and these are the limits for the hysteresis parameters.

   Figure 7. The simulation controller block diagram. Controller includes the current controller (inner loop) and the voltage control loop (PI-control), where together they present

   SMC

   Figure 8. Simulation model of SMC control with split capacitor type elementary additional series positive output super lift converter

5. Simulation Results

   The validation of the system performance is done for five regions viz. transient region, line variations, load variations, steady state region and also component variations.

   Table 2.Parameters Of Split Capacitor Type Elementary Additional Series Positive Output Super Lift Converter

   Parameters Name	Symbol	Value
   Input Voltage	Vin	12V
   Output Voltage	Vo	72V
   Inductor	L	100H
   Capacitors	C1 to C5	30F
   Nominal switching frequency	fs	100kHz
   Load Resistance	R	50
   Range of duty cycle	k	0.3 to 0.9
   Desired duty cycle	k	0.5

   1. Transient Region

      Figure 9 shows the output voltage and the inductor current of PI with POESLLC in the transient region. It can be found that the converter output voltage and inductor current has a negligible overshoot and settled at time of

      Inductor Current(A)

      0.037 s in this region with designed PI control.

      Output Voltage (V)

      Time (s)

      Time (s)

      Figure 9. Inductor current and Output voltage in a transient region with PI Control

      Output Voltage (V)

      Inductor Current(A)

      Time (s)

      Time (s)

      Figure 10. Inductor current and Output voltage in a transient region with SMC Control

      Figure 10 shows the output voltage and the inductor current of SMC with POESLLC in the transient region. It can be found that the converter output voltage and inductor current has a negligible overshoot and settled at time of

      0.012 s in this region with designed SMC control

      Table 3.Output Voltage And Inductor Current Of Poesllc Converter Parameters With Both Pi And Smc In Transient Region

      	PI Control		SMC Control
      	Settlin g time	Maximum overshoot	Settlin g time	Maximu m overshoo t
      Output voltage	0.037s	No	0.012s	No
      Inductor current	0.037s	0.55 A	0.012s	0.15 A

      Table 3 shows the comparison between the two models in transient region. The output voltage of POSELLC converter with PI has no overshoot, while the output voltage of the same converter with SMC has no overshoot. The gain of the output voltage with SMC can be reduced by increasing the gain but it will increase the settling time. The graphs show that the settling time with PI is longer. For POSELLC converter with SMC, the settling time is shorter but the inductor current has much less overshoot. SMC has shorter settling time in this region the inductor current has much less overshoot.

   2. Line Variations

      Output Voltage (V)

      In Figure 11 shows the variation of output voltage of PI control with split capacitor type positive output elementary additional series positive output super lift converter for the input voltage step change from 12 V to 9V ( – 30 % line disturbance). It can be found that converter output voltage has a maximum overshoot of 16 V and 0.02 s settling time with designed PI control. In Figure 12 sows the variation of output voltage of PI control with split capacitor type elementary additional series positive output super lift converter for the input voltage step change from 12 V to 15V ( + 30 % line disturbance). It can be found that converter output voltage has a maximum overshoot of 18 V and 0.028 s settling time with designed PI control.

      Time (s)

      Output Voltage (V)

      Figure 11. Output voltage when input takes a step change from 12 V to 9 V with PI control

      Time (s)

      Figure 12. Output voltage when input takes a step change from 12 V to 15 V using PI control

      Output Voltage (V)

      Time (s)

      Output Voltage (V)

      Figure 13. Output voltage when input takes a step change from 12 V to 9 V using SMC control

      Time (s)

      Figure 14. Output voltage when input takes a step change from 12 V to 15 V with SMC control

      In Figure 13 shows the variation of output voltage of SMC control with split capacitor type positive output elementary additional series positive output super lift converter for the input voltage step change from 12 V to 9V ( – 30 % line disturbance). It can be found that converter output voltage has a maximum overshoot of 5 V and 0.005 s settling time with designed SMC control. In Figure 14 shows the variation of output voltage of SMC control with split capacitor type elementary additional series positive output super lift converter for the input voltage step change from 12 V to 15V ( + 30 % line disturbance). It can be found that converter output voltage has a maximum overshoot of 8 V and 0.008 s settling time with designed SMC control. The POSELLC converter model with SMC has almost negligible effect. It shows that SMC has a strong immunity against line variation disturbances, and has better performance than PI control in this region.

      Table 4.Output Voltage Of Poesllc Converter Parameters With Both Pi And Smc In Line Variation

      	PI Control		SMC Control
      	Settlin g time	Maximum overshoot	Settlin g time	Maximu m overshoo t
      Output Voltage (12 Vto 9 V)	0.02s	16 V	0.005s	5 V
      Output Voltage (12 Vto 15 V)	0.028s	18 V	0.008s	8 V

   3. Load Variations

      Output Voltage (V)

      Figure 15 shows variation of output voltage with step change in load from 50 to 60 (+ 20 % load disturbance) using PI control. It could be seen that there is a small overshoot of 0.5V and steady state reached with a very less time of 0.003 s.

      Time (s)

      Figure 15. Output voltage when load resistance makes a step changes from 50 to 60

      using PI control

      Output Voltage (V)

      In Figure 16 shows another variation of output voltage with step change in load from 50 to 40 ( – 20 % load disturbance ) using PI control. It could be seen that there is a small overshoot of 0.5 V and steady state reached with very small time of 0.004 s.

      Time (s)

      Figure 16. Output voltage when load resistance

      Output Voltage (V)

      makes a step changes from 50 to 40 using PI control.

      Figure 17 Output voltage when load resistance makes a step changes from 50 to 60

      using SMC control

      Figure 17 shows the variation of output voltage with the step change in load from 50 to 60 ( + 20

      Time (s)

      Time (s)

      Output Voltage (V)

      % load disturbance ) using SMC control. It could be seen that there is a overshoot of 3 V and steady state is reached with a very less time of 0.008 s

      Time (s)

      Figure 18. Output voltages when load resistance makes a step changes from 50 to 40

      using SMC control

      In Figure 18 shows another variation of output voltage with step change in load from 50 to 40 (- 20 % load disturbance) using SMC control. It could be seen that there is a overshoot of 3 V and steady state is reached with a very small time of

      0.007 s.

      Table 5.Output Voltage Of Poesllc Converter Parameters With Both Pi And Smc In Load

      Variation

   4. Steady State Region

      Inductor Current (A)

      Figure 19 shows the instantaneous output voltage and current of the inductor current in the steady state It is evident from the figure that the output voltage ripple is very small about 0.45V and the peak to peak inductor current is 0.55A while the switching frequency is 100 kHz.(using PI control)

      Output Voltage (V)

      Time (s)

      Time (s)

      Figure 19. Output voltage and inductor current in steady state region using PI control

      Table 6.Output Voltage And Inductor Current Of Poesllc Converter Parameters With Both Pi And Smc In Load Variation

      	PI Control		SMC Control
      	Settlin g time	Maximum overshoot	Settlin g time	Maximu m overshoo t
      Output Voltage 50 to 60	0.003s	0.5 V	0.008s	3 V
      Output Voltage 50 to 40	0.004s	0.5 V	0.007s	3 V

      Figure 20 shows the instantaneous output voltage and current of the inductor current in the steady state It is evident from the figure that the output voltage ripple is very small about 0.11V and the peak to peak inductor current is 0.15A while the switching frequency is 100 kHz.(using SMC control)

      Inductor Current (A)

      Output Voltage (V)

      Time (s)

      	PI Control		SMC Control
      	Peak to Peak ripple current	Peak to Peak ripple voltage	Peak to Peak ripple current	Peak to Peak ripple voltage
      Output voltage		0.45 V		0.11 V
      Inductor current	0.55 A		0.15 A

      Time (s)

      Figure 20. Output voltage and inductor current in steady state region using SMC control

   5. Circuit Components Variations

      An interesting result has been illustrated in Figure 21, which shows response for the variation in capacitor value from 30 F to 120 F. There is no wide variation in the output peak overshoot and settling time. The capacitor change has no severe effect on the steady state voltage across the load. In

      Figure 22 shows the output voltage for inductor variation from 100 H to 300 H and the change has no severe effect on the converter behavior due to the efficient developed PI control.

      An interesting result has been illustrated in Figure 23, which shows response for the variation in capacitor value from 30 F to 120 F. There is no wide variation in the output peak overshoot and settling time. The capacitor change has no severe effect on the steady state voltage across the load. In Figure 24 shows the output voltage for inductor variation from 100 H to 300 H and the change has

      converter b MC control.

      no severe effect on the ehavior due to the

      Figure 23. Output voltage when capacitors variation from 30 F to 120F

      An interesting result has been illustrated in Figure 23, which shows response for the variation in capacitor value from 30 F to 120 F. There is no wide variation in the output peak overshoot and

      efficient developed S

      Time (s)

      settling time. The capacitor change has no severe effect on the steady state voltage across the load. In Figure 24 shows the output voltage for inductor variation from100 H to 300 H and the change has no severe effect on the converter behavior due to the efficient developed SMC control.

6. Comparison of Output Voltage in Various Topologies of DC/DC Converters

   Output Voltage (V)

   Time (s)

   Output Voltage (V)

   Figure 21. Output voltage when capacitors variation from 30 F to 120F

   Output Voltage (V)

   Time (s)

   Figure 22. Output voltage when inductor varies

   from 100 H to 300 H

   Table 3 shows the comparison of voltage transfer gain for different topologies of DC / DC converter with a varying duty cycle for an input voltage of 12

   V. Graphical representation of output voltage versus duty cycle for different topology of DC / DC converter are shown in Fig 25.

   	Duty Cycle
   Types of Converters	0.5	0.6	0.7	0.8	0.9
   Boost Converter	2	2.5	3.33	5	10
   Positive Output Super lift Elementary main series converter	3	3.5	4.33	6	11
   Positive Output Super lift Elementary additional series converter	5	6	7.66	11	21

   Table 7.Comparison Of Voltage Transfer Gain In Various Topologies Of Dc/Dc Converters

   www.ijert.org 9

   Split Capacitor type positive output elementary additional series super lift converter

   6

   7

   8.66

   12

   22

   8. References

   1. F.L.Luo and H.Ye, Positive output super lift converters, IEEE Transaction on power electronics, Vol.18, No. 1, pp. 105-113, January 2003.

   2. LUO F.L., Luo converters voltage lift technique, Proceedings of the IEEE Power Electronics special conference IEEE-PESC98,Fukuoka, Japan, 17-22, pp. 1783-1789, May. 1998.

      Output Voltage (V)

   3. LUO F.L., Luo converters voltage lift technique (negative output), Proceedings of the second World Energy System international conference WES98, Tornoto, Canada, 19-22, pp.253-260, May. 1998.

   4. LUO, F.L.: Re-lift converter: design, test, simulation and stability analysis, IEE Proc.Electr. Power Appl., 1998, 145, (4), pp. 315-325.

   5. R.Middlebrook and S.Cuk, A General Unified Approach to Modeling Switching-Converter Power Stages, International Journal of Electronics, Vol.42, No.6, pp. 521-550, June. 1977.

      Duty Cycle

      Figure 25. Graphical representation of output voltage Vs duty cycle in various topologies

      of DC/DC converters

7. Conclusions

The split capacitor type elementary additional series positive output super lift converter was tested in steady state region, transient region (turn on), under line variation, and under load variation. These tests where done for the POSELLC converter using two different control techniques, the traditional PI control and the SMC. In steady state both models showed similar characteristics. For dynamic tests the SMC showed to be more efficient against disturbances than the PI control. The settling time was longer in case of SMC also a higher output voltage overshoot. On the other hand, the inductor current didnt have high overshot while it had high inductor current overshoot with PI control. The reduced current overshoot is due to the additional inductor current feedback. The SMC is showing a promising future in the application of switch mode power supply because it is a non linear control and can evaluate the non linearity of the converter components. Second, it isnt operating at a constant switching frequency. Third, its easer to design a converter with SMC than PI control.

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