Implementation of Carry Look-Ahead in Domino Logic

Implementation of Carry Look-Ahead in Domino Logic

1. Vijayakumar1 M. Poorani Swasthika2 S. Valarmathi3 And A. Vidhyasekar4

   1, 2, 3 Master of Engineering (VLSI design) & 4Asst.Prof/ Dept.of ECE Akshaya College of Engineering and Technology, Coimbatore, India

   Abstract: In this brief, an efficient implementation of an 8-bit Manchester carry chain (MCC) adder in multi output domino CMOS logic has been proposed. The carries of this adder are computed in the parallel by two independent 4-bit carry chains. Due to its finite carry chain length, the advantage of the proposed 8-bit adder module for the implementation of wider adders leads to significant operating speed improvement compared to the corresponding adders based on the standard 4-bit MCC adder module.

   Keywords: carry look-ahead (CLA) adders, Manchester carry chain, multi output domino logic.

   1. INTRODUCTION

      Addition is the most commonly used arithmetic operation and also the speed limiting element to make faster VLSI processor. As the demand for higher performance processor grows. there is a continuing need to improve the performance of arithmetic units and to increase their functionality. High-speed adder architectures include the carry look- ahead (CLA) adders, carry-skip adders, carry-select adders, conditional sum adders, and combinations of these structures [1][4]. High-speed adders based on the CLA principle remain dominant, since the carry delay can be improved by calculating each stage in parallel. The CLA algorithm was first introduced in [5], and several variants have been developed. The Manchester carry chain (MCC) is the most common dynamic (domino) CLA adder architecture with a regular, fast, and simple structure adequate for implementation in VLSI [6], [7]. The recursive properties of the carries in MCC have enabled the development of multi output domino gates, which have shown areaspeed improvements with respect to single- output gates.

      In this brief, a new 8-bit carry chain adder block in multi output domino CMOS logic is proposed. The even and odd carries of this adder are computed in parallel by two independent 4-bit carry chains. Implementation of wider adders based on the use of the proposed 8-bit adder module shows significant operating speed improvement compared to their corresponding adders based on the standard 4-bit MCC adder module.

      This brief is organized as follows. In Section II, Preliminary concepts on the domino design of MCC adders are given. In Section III, the architecture of the proposed double carry chain 8-bit MCC adder is presented. In Section IV, comparisons among the proposed MCC design and two conventional MCC topologies in the open literature are given. Finally, in Section V, the conclusions are drawn.

   2. PRELIMINARY CONCEPTS AND PREVIOUS WORK

      Let A = an1an2 · · · a1a0 and B = bn1bn2 · · · b1b0 rep-resent two binary numbers to be added and S = sn1sn2 · · ·s1s0 be their sum. In the following, the symbols ·, +, , and are used to denote the AND, INCLUSIVE OR, EXCLUSIVE OR, and

      NOT logical operations, respectively. In binary addition, the computation of the carry signals is based on the following recursive formula:

      ci=gi+zi.ci-1 (1)

      Where gi = ai · bi and zi are the carry generate and the carry propagate terms, respectively. The latter, for the case of INCLUSIVE OR adders, is defined as zi = ti = ai + bi, while for the case of EXCLUSIVE OR adders, it is defined as zi = pi = ai

      bi. In Fig. 1, the implementation of the generate

      and the two types of propagate signals in domino CMOS logic is shown.

      Expanding relation (1), each carry bit ci can be expressed as

      ci = gi + zigi1 + zizi1gi2 + · · · + zizi1 · ·z1g0

      + zizi1 · · · z0c1. (2)

      The sum bits of the adder are defined as si = pi

      ci1, where c1 is the input carry.

      The MCC [6], [7] generates all the carries computed accord-ing to relation (2) in parallel, using an iterative shared transistor structure. In practice, the CLA length is limited to four in order to cut down the number of series-connected transistors. Fig. 2 shows the conventional implementation of the

      4-bit carry chain using multi output domino CMOS logic.

      MCC adders are EXCLUSIVE OR adders propagate signal is defined as zi = pi = ai bi, to avoid false discharges produced at the output nodes of the carry chain due to higher ORAND forms of multi output gates.

      For the implementation of the sum signals, the domino chain is terminated, and the sum bits of the MCC adder are implemented using static CMOS XOR gates [6], the design of which is shown in Fig. 3.

      Several variations of the MCC adder in domino CMOS logic have been proposed in the literature [6]. Moreover, static CMOS MCC implementations are also given . Among them, a high-speed design has been proposed in. where the MCC is supported by the carry-skip capability to improve performance.

      Fig. 1. Domino implementation for the (a) generate, (b) XOR

      propagate, and (c) OR propagate signals.

      Fig. 2. Conventional domino 4-bit MCC

      Fig. 3. Static CMOS implementation of the XOR gate for the sum computation

   3. NEW HIGH-SPEED DOUBLE CARRY CHAIN

      ADDERS

      MCC adders can efficiently be designed in CMOS logic. As mentioned previously, due to technological constraints[10], the length of their carry chains is limited to 4 bits. However, these 4-bit adder blocks are used extensively in the literature [2], [7], in the design of wiIdVe.r adders.

      In the following, we propose the design of an 8-bit adder module which is composed of two independent carry chains. These chains have the same length (measured as the maxi-mum number of series-connected transistors) as the 4-bit MCC adders. According to our simulation results, the use of the proposed 8-bit adder as the basic block, instead of the 4-bit MCC adder, can lead to high- speed adder implementations.

      V.

      The derived here carry equations are similar to

      those for the Ling carries proposed. The derived carry equations allow the even carries to be computed separately of the odd ones. This separation allows the implementation of the carries by two independent 4-bit carry chains; one chain computes the even carries, while the other chain computes the odd carries. In the following, the design of the proposed 8-bit MCC adder is analytically presented.

      1. Even Carry Computation

         For i = 0 and z0 = t0, from relation (1), we get that c0 = g0 + t0 · c1. Since the relation gi = gi · ti holds, we get that c0 = t0 · (g0 + c1) = t0 · h0, where h0 = g0 + c1 is the new carry.

         From relation (2), for i = 2 and zi = pi, we get that

         c2 = g2 + p2g1 + p2p1g0 + p2p1p0c1.

         Since gi + pi · gi1 = gi + ti · gi1 and pi = pi · ti, we have c2 = t2(g2 + g1 + p2p1g0 + p2p1p0c1)

         = t2 (g2 + g1 + p2p1t0 (g0 + c1)) = t2 · p Where

         p = g2 + g1 + p2p1t0 (g0 + c1)

         is the new carry.

         In the same way, the new carries for i = 4, 6 are computed as

         h4 = g4 + g3 + p4p3t2 (g2 + g1 + p2p1t0 (g0 +

         c1))

         p = g6 + g5 + p6p5t4 x (g4 + g3 + p4p3t2 (g2

         + g1 + p2p1t0 (g0 + c1))) .

      2. Odd Carry Computation

      The new carries for the odd values of i are computed according to the aforementioned methodology proposed for the even carries as follows:

      p = g1 + g0 + p1p0c1

      p = g3 + g2 + p3p2t1 (g1 + g0 + p1p0c1)

      p = g5 +g4 +p5p4t3 (g3 + g2 + p3p2t1 (g1 + g0

      +p1p0c1))

      h7 = g7 + g6 + p7p6t4 *(g5 + g4 + p5p4t3 (g3 + g2 + p3p2t1 (g1 + g0 + p1p0c1)))

      Let Gi= gi + gi1 and Pi = pi · pi1 · ti2 be the new generate and propagate signals, respectively, where g1 = c1

      Fig. 4. Proposed carries implementation for (a) the even carry

      chain and (b) the odd carry chain.

      Fig. 5. New (a) generate and (b) propagate signals implemented in domino CMOS logic.

      Fig. 6. Sum bit implementation

      and t1 = 1. Then, the following equations are derived for the new carries for even values of i:

      p = G2 + P2G0

      h4 = G4 + P4G2 + P4P2G0

      p = G6 + P6G4 + P6P4G2 + P6P4P2G0

      Fig. 7. Static CMOS implementation of the 2 1 multiplexer.

      While for odd values of i, the equations for the new carries are rewritten as follows:

      proposed carries for the computation of the sum bits according to (3).

      p = G1

      + P1c1

      For the implementation of the sum signals, the domino chain is terminated, and static CMOS

      p = G3 + P3G1 + P3P1c1

      p = G5 + P5G3 + P5P3G1 + P5P3P1c1

      h7 = G7 + P7G5 + P7P5G3 + P7P5P3G1 + P7P5P3P1c1.

      Fig. 8. Ripple carry chains based on (a) the proposed 8-bit MCC adder module and (b) the conventional 4-bit MCC adder module.

      From the aforementioned equations, it is evident that the groups of even and odd new carries can be computed in parallel by different carry chains in multi output domino CMOS logic, as shown in Fig. 4.

      The new generate and propagate signals Gi and Pi can be easily proven to be mutually exclusive, avoiding false node discharges. Their domino CMOS implementation is shown in Fig. 5.

      Between the new and the conventional carries,

      ci1 = ti1

      hi1 holds; therefore, the sum bits are computed as si

      = pi (ti1 hi1). the computation of the sum bits can be performed as follows:

      si = hi1 pi + hi1 (pi ti1) (3)

      for i > 0, while s0 = p0 c1.

      Relation (3) can be implemented using a 2

      1. multiplexer that selects either pi or pi ti1

         according to the value of hi1, as shown in Fig. 6.

         Taking into account that an XOR gate introduces equal delay with a 2 1 multiplexer and both terms pi and pi ti1 are computed faster than

         hi, then no extra delay is introduced by the use of the

         technology is used for the pi ti1 gate and the final

      2. 1 multiplexer. The design of the XOR gate in Fig. 6 is similar to that in Fig. 3. An efficient static

      CMOS implementation of the 21 multiplexer is shown in Fig. 7.

   4. MCC DESIGN ISSUES AND COMPARISONS

      To evaluate the speed performance of the proposed (PROP) design over the conventional (CONV) one, 8-, 16-, 32-, and 64-bit adders have been designed according to the carry chain principle given in Fig. 8(a) and (b), respectively, and simulated using SPECTRE in a standard 90-nm CMOS technology (VDD = 1 V). The conventional 8-, 16-, 32-, and 64-bit MCC adders are designed by cascading two, four, eight, and sixteen 4-bit MCC adder modules, respectively. The proposed 16-, 32-, and 64-bit MCC adders are designed by cascading two, four, and eight of the proposed 8-bit MCC adder modules, respectively.

      TABLE I

      CARRY PROPAGATION DELAY TIMES AND PERCENTAGE IMPROVEMENTS

      	PROP(ps)	CONV(ps)	PERCENTAGE (%)
      8-bit	215.50	226.21	4.73
      16-bit	352.40	458.15	23.08
      32-bit	616.92	881.93	30.05
      64-bit	1115.44	1718.20	35.08

      The simulation results, for the carry propagation delays, are presented in Table I. The PROP design provides a performance improvement of 4.73% over the CONV design for the 8-bit adder. The performance improvements of the PROP design over the CONV design are 23.08% for the 16-bit adder, 30.05% for the 32-bit adder, and 35.08% for the 64-bit adder. Simulated waveforms of the carry signals (C7, C15, C23, and C31) for the proposed 32- bit adder are presented in Fig. 9. In all cases previously mentioned, the average energy consumption for a computation is increased by 43.4% for the PROP design with respect to the CONV one, while the area overhead is 49.9%, due to the extra gates that are required for the implementation of the ti and the new generate (Gi) and propagate (Pi) signals. The proposed technique can be exploited in the design of arithmetic circuits where high performance is required at the expense of power consumption.

      As referred previously, a modified high-speed design of the 4-bit MCC adder module has been proposed, where the MCC is supported by the carry- skip capability to improve performance. The same technique can also be applied to the chain which computes the odd carries of the proposed 8-bit adder to further improve its efficiency. Since the 8-bit adder is the building block for higher bit adders, in all cases, the performance is proportionally improved. However, even without this addition, the proposed topology outperforms the modified MCC design proposed in since it provides 7.18%, 11.79%, 17.59%, and 23.04% speed improvements for the 8-, 16-, 32-, and 64-bit adders, respectively, as it is presented in Table II. Moreover, in Fig. 10, a graphical presentation of the carry propagation delays with respect to the number of bits in the adder among the three design styles (PROP, CONV, is given.

      Fig. 9. Carry signal simulated waveforms for the proposed 32-bit adder.

      TABLE II

      CARRY PROPAGATION TIMES AND PERCENTAGE IMPROVEMENTS

      	PROP(ps)	[12](ps)	PERCENTAGE (%)
      8-bit	215.50	232.18	7.18
      16-bit	352.40	399.51	11.79
      32-bit	616.92	748.60	17.59
      64-bit	1115.44	1449.36	23.04

      Fig. 10. Carry propagation delay with respect to the number of bits.

   5. CONCLUSION

The MCC is an efficient and widely accepted design approach to construct CLA adders. In this brief, we have presented a new Manchester design style that is based on two independent carry chains. Each chain computes, in parallel with the other, half of the carries. In this way, the speed performance is significantly improved with respect to that of the standard MCC topology. The proposed design technique has been applied for the implementation of 8-, 16-, 32-, and 64-bit adders in multi output domino logic, and the simulation results verified its efficiency.

ACKNOWLEDGMENT

The authors would thank Prof. R. Subramanian, Associate professor, Department of EEE, Akshaya College of engineering and technology for his valuable suggestions and contributions. They would also like to thank the anonymous reviewers of IJERT.

REFERENCES

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G. Vijayakumar received the B.E degree in Electronics and Communication Engineering from Coimbatore Institute of Engineering and Technology, Coimbatore in the year 2011. He is currently doing ME degree in VLSI Design from Akshaya College of Engineering and Technology, Coimbatore. Presently he is doing PG project on low power VLSI. His research

interests are low power VLSI Circuits, communication systems, Power optimization of CAD circuits.

M. Poorani Swasthika received her B.E. degree in Electrical and Electronics Engineering from Dr.Mahalingam College of Engineering and Technology, Pollachi in the year 2010. she is currently doing ME degree in VLSI Design from Akshaya College of Engineering and Technology, Coimbatore.

Presently She is doing PG project on low power VLSI. Her research interests are low power VLSI Circuits, power systems, Power optimization of CAD circuits.

S.Valarmathi received the B.E degree in Electronics and Communication Engineering from VSB College of Engineering, Karur in the year 2012. She is currently doing ME degree in VLSI Design from Akshaya College of Engineering and Technology, Coimbatore. Presently she is doing PG project on low power VLSI. Her research interests are low

power VLSI Circuits, Power optimization of CAD circuits.

A. Vidhyasekar received the B.E degree in Electronics and Communication Engineering from M.P.Nachimuthu M.Jaganathan Engineering College, Erode in the year 2005 and M.E degree in VLSI Design from Karpagam college of Engineering, Coimbatore in the year 2011. He is Presently he is working as an Assistant professor in the

Department of Electronics and Communication Engineering at Akshaya College of Engineering and Technology, Coimbatore. His research interests are Low power system control and operation, Low power VLSI Circuits.