Leakage Analysis for Low Power Quasi-Adiabatic Architectures using Semi-Custom Design

Leakage Analysis for Low Power Quasi-Adiabatic Architectures using Semi-Custom Design

Ms. K. Jayanthi

Department of Electrical and Electronics Engineerinng Mepco Schlenk Engineering College

Sivakasi, India

Abstract There exist a number of methods to reduce power dissipation. The most common is to reduce the power supply voltage. Adiabatic charging and discharging of capacitors can accomplish significant reduction in switching power dissipation. The term energy recovery depicts the nature of the circuits which recover a portion of the energy that is stored in the capacitances during computation, and recycle the energy for subsequent computations. These circuits offer significant reduction in power dissipation when compared with conventional static CMOS design. However, limited number of literatures is found so far in regard to the leakage effects in adiabatic circuits, though there has been a plethora of circuits using conventional CMOS design. This work presents the analysis of leakage power in the widely published 2N2P, 2N2N2P, PFAL, IPGL quasi-adiabatic circuits. The influence of the threshold voltage on leakage current and the method of reducing the same are presented. Analysis is done for different (W/L) ratios of the PMOS transistors that form the charge/recovery path of the adiabatic circuits, across a wide frequency and supply voltage range. The PMOS transistor size affects the speed of response, the output load capacitance, the maximum adiabatic frequency range, the Adiabatic Gain of the circuit and the layout area of the circuits. Simulation is done by varying the frequency around 500 MHz and supply voltage around 3.3V. The simulation is done and verified by using Tanner Spice Simulator using the AMS350nm process models obtained from Austria Microsystems.

The power consumption is the most important decisive factor for the design and enhancement of portable and high performance applications. Hence, the growth have be on the road to look at for techniques to reduce the power dissipation, low power operation, and designing for energy recovery and recycling. Energy recovery technique proves to be a potential approach for the design of low power VLSI circuits. The most important advantage of adiabatic circuits results from its inherent nature of deriving a constant current from the power clock and the FETs working with minimum voltage between its source and drain terminals. These circuits are classified into fully adiabatic and quasi-adiabatic circuits, based on whether full energy recovery or partial energy recovery is obtained in the process.

1. ADIABATIC SWITCHING CIRCUITS Adiabatic switching is a new approach for reducing power

   dissipation in digital logic. When adiabatic switching is used, the signal energies stored on circuit capacitances may be recycled instead of dissipated as heat [1]. For an energy recovery circuit, the ideal energy dissipated when a capacitance C is charged from zero to Vdd, or discharged from Vdd through a circuit of resistance R during time T is given by

   CV 2 RC

   E I 2RT dd RT CV 2

   (2)

   Keywords Adiabatic Circuits; Charge Recovery Logic; Leakage Power.

   diss

   T

   T dd

   1. INTRODUCTION

      The importance of reducing power dissipation in digital systems is increasing as the range and sophistication of applications in portable and embedded computing continues to

      when the time T >> RC, the energy dissipation is much smaller than that occurring in the conventional complementary metal oxide semiconductor (CMOS) circuit, for which an

      CV 2

      increase. System-level issues such as battery life, weight, and size are directly affected by power dissipation. Inroads into

      energy of

      dd

      2

      is required during a charge and an equal

      reducing power dissipation of the digital systems only serve to improve the performance and capabilities of these systems.

      Power dissipation in static CMOS circuits consists of dynamic and static power components. The dynamic power is due to charging and discharging of node capacitance and is defined by

      amount during the discharge cycle. As a result, when the

      charging time T is much larger than the RC time constant, the power consumption can be reduced.

      A variety of adiabatic logic architectures has been proposed for low power VLSI design [2][5]. Most of them use diodes or diode like devices for precharge, which causes inevitable energy loss due to the voltage drop across the

      L

      P C V 2 f

      (1)

      diodes. Other designs have been projected to purge the precharge diode; however, they have potential problems of

      The static power is due to leakage currents and current

      drawn from the supply voltage. The power dissipation in conventional CMOS circuits can be reduced by reducing the decreasing the value of capacitance (C) or the supply voltage

      (V) [1] between the logic high and the logic low levels.

      floating output nodes and faulty logic [5]. The literatures have brought out several types of adiabatic circuits namely, 2N-2P, 2N-2N2P, PFAL, Improved Pass-gate Adiabatic Logic (IPGL). The Efficient Charge Recovery Logic ECRL [2] of 2N2P structure, which is generally used as a reference for evaluating the power dissipation of a new-fangled logic

      family. Figure 1 (a) shows the structure of 2N2P buffer using two cross-coupled pMOS for precharge and recovery. This

      tp

      logic exhibits a non-adiabatic loss proportional to CV 2 , where

      Vtp is the threshold voltage of pMOS devices in the cross coupled transistor pair. The non-adiabatic dissipation occurs during a brief interval in the beginning of the evaluation phase [2].The 2N-2N2P logic as shown in Figure 1(b) derived from 2N2P, for the comparative advantage of eliminating the cross- coupled NMOS switching resulting in non-floating outputs for large part of the recovery phase. These devices present a balanced capacitive load and have better speed characteristics.

      transistors and gate leakage power caused by carrier tunneling through the thin gate oxides.

      The most effective way to reduce the power dissipation is to lower the supply voltage. With the scaling of supply voltage and device dimensions, the transistor threshold voltage also be scaled in order to achieve the required performance. This is because of the decrease in propagation delay when the threshold voltage reduces. As a result, it will increase the leakage current. Due to the exponential nature of leakage current in the subthreshold regime of the transistor, leakage current can no longer be ignored. The transistor off-state current (Ioff) is the drain current when the gate-to-source voltage is zero. Ioff is greatly affected by threshold voltage, channel length, channel width, depletion width beneath the channel area, channel/surface doping profiles, drain/source junction depths, gate oxide thickness, supply voltage and the junction temperature.

      The subthreshold leakage current plays a dominant role when the device size is below 0.5µm. The subthreshold leakage current can be expressed as

      Where

      Ileak I0 exp Vgs Vth /VT

      T

      I0 0Cox W LV 2e1.8

      (4)

      (5)

      Fig 1 Schematic of Adiabatic circuit families

2. LEAKAGE POWER ANALYSIS OF ADIABATIC

   where is the subthreshold slope factor, VT is the thermal voltage, and µp is the mobility of the pMOS transistor in the charging path, µ is the mobility of the leaking nMOS/pMOS transistor, Vgs is the gate to source voltage, Cox is the gate oxide capacitance and W and L arethe channel width and length of the transistor under consideration.

   The leakage current, due to subthreshold conduction, is computed from Ileak when Vgs=0. Then

   CIRCUITS

   Ileak I0 exp Vth V

   (6)

   Figure 1 depict the leak model [6] of adiabatic circuits such as 2N2P, 2N-2N2P, PFAL, IPGL. Consider the leak model of 2N2P Buffer as shown in Figure 1(a) the two cross coupled pMOS, MP1 and MP2 provides output charging/discharging for evaluation and recovery processes. When the IN is rising and reaches the threshold voltage, MN1 conducts and makes the OUT low. Simultaneously PC rises and turns MP2 ON with node /OUT rising with PC. At that time, MP1 does not

   T

   The non-adiabatic energy due to leakage current is expressed by PLeak Vdd IleakkT where k is the number of phases per cycle when leakage current flows through the device. Then the total energy dissipation per full charge-

   discharge cycle including the leakage loss is

   2R C 1

   conduct because it is operating in weak inversion region i.e.

   Ediss on L C V 2

   C V 2

   V I

   kT E

   (7)

   Vth<Vgs, so it has some amount of subthreshold leakage

   T L dd

   2 L th. p

   dd leak

   opn

   current. The transistor MN2 passes negligible leakage current due to body effect posed by stacking nMOS transistor [7].

   The power dissipation components of a CMOS circuit is

   1

   2

   Ediss

   2C 2V 2

   L dd

   L th, p

   C V

   given by

   T P W L p Vdd Vth. p 2

   (8)

   PCMOS Pswitching Pshort_ circuit Pleak

   V C W V 2 exp Vgs Vth kT E

   L dd sc leak

   PCMOS C V 2 P P

   (3)

   dd ox L T

   VT

   opn

   Where Psc is the power dissipation due to short circuit current and Pleak is a combination of the subthreshold leakage power due to non-ideal off-state characteristics of the MOS

   From the above Equations (8), the third term is mainly contributed by subthreshold current. It increases exponentially with increasing threshold voltage and also for different technologies. The more number of wider transistors constitutes

   the leakage path, the leakage current increases. From Equation

   (8) it can be inferred that the leakage current is directly proportional to (i) (W/L) x the number of parallel transistors,

   (ii) Vdd (iii) exp (Vgs – Vth), (iv) T.

   Various design techniques [8] are used to reduce the subthreshold leakage current is (i) by varying the size of the transistors (ii) by varying the threshold voltage. Multiple threshold CMOS circuit technologies can be used to deal with the leakage problem. These circuits have both high and low threshold transistors in a single chip. The high threshold transistors can suppress the subthreshold leakage current, while the low threshold transistors are used to achieve the high performance.

3. SIMULATION AND RESULTS

   The adiabatic circuits are simulated using standard BSIM3V3 model parameters. Figures 2 (a) and (b) show the effect of different (W/L) ratios on leakage current. The (W/L) ratio for the graphs shown in Figure 2 (a) is WP=9µm and (b) is WP=6µm for Vdd=2.5V. L=0.5um was assumed for the simulations. From the graphs it is observed that for increased value of frequency, the leakage current increases as per Equation (5).

   (a)

   (b)

   Fig 2 (a) , (b) Effect of (W/L) ratio on Leakage Current for various Frequency when Vdd=2.5V

   Table.1 shows the leakage current for adiabatic buffer against the conventional CMOS buffer for different Frequencies with various (W/L) ratio of pMOS transistor and Vdd. The supply voltage can be varied from 2V to 3.3V. On comparing Figure 2 (a) and (b) the leakage current will increase on increasing the (W/L) ratio of the MOS transistors. In this, leakage current will be increased approximately 42.86%.

   Figure 3 (a) shows the comparison of average power of various adiabatic circuits against conventional CMOS for different frequencies. Figure 3 (b) shows the average power comparison of adiabatic circuits. Figure 3(c) shows the average power of conventional CMOS circuits. The average power keeps on increasing when the frequency increases. Figure 4 shows the effect of threshold voltage on Leakage current. From the graph, it is observed that the subthreshold leakage current decreases on increasing the value of threshold voltage of leak transistor because it is directly proportional to exp (Vgs-Vth).

   Fig 3 (a) Average Power comparison of 2N2P, 2N2N2P, PFAL, IPGL and CMOS for various Frequencies

   Table.1 Leakage Current for Adiabatic Buffer against Conventional CMOS Buffer for Vdd=2.5v

   State	Adiabatic Circuits(µA)				CMOS (mA)	(W/L)p (µm)	Freq
   	2N2N	2N2N2P	PFAL	IPGL
   0	-2.61	-0.832	-3.18	-1.21	0.0821	(6/.5)	500MHz
   1	-3.14	-3.09	-3.13	-2.72	-0.173
   0	-2.67	-0.868	-18.9	-1.43	0.0983	(9/.5)
   1	-3.83	-4.45	-5.67	-4.11	-0.223
   0	-1.25	-0.275	-2.34	-1.83	0.0798	(6/.5)	250MHz
   1	-1.27	-1.07	-1.09	-1.35	-0.179
   0	-1.87	-0.279	-1.28	-0.432	.096	(9/.5)
   1	-1.86	-1.62	-1.55	-1.18	-0.223
   0	-.633	-0.321	-0.407	-0.594	0.0681	(6/.5)	100MHz
   1	-0.652	-0.422	-0.40	-0.655	-0.134
   0	-.0153	-0609	-0.617	-0.938	0.0698	(9/.5)
   1	-0.633	-0.620	-0.611	-0.235	-0.155

   parameters, the I0 value is calculated. The following parameters are used to calculate I0: µ0=129e-8µm2/V-s, Vgs=Vdd/2 and Vth=0.6915v for varying Vdd from 2V to 3.3V.

   Figure 6 shows the effect of Vdd on Leakage power. From the graph, it is observed that, the leakage power increases linearly with respect to Vdd because it is directly proportional to ILeak. The graph is drawn by using the Equation (7).

   Fig 3 (b) Average Power comparison of 2N2P, 2N2N2P, PFAL, IPGL for various

   Frequencies.

   Fig 4 Effect of Threshold Voltage on Leakage Current

   Fig 3 (c) Average Power for conventional CMOS for various Frequencies.

   Figure 4 is drawn using the Equation (6).The value of Vth, p have been taken around in the range of 0.2Vdd<Vth<0.5Vdd. The threshold voltage of 0.6912V is taken into account for analysis purpose. The subthreshold leakage current can be reduced by varying the size of the transistor or by increasing the threshold voltage.

   Figure 5 shows how the leakage current is varied for various (Wp) values. This graph is computed using the Equation (5). Using the standard BSIMV3 model

   Fig 5 Effect of Width (W) on Leakage current

   Fig 6 Effect of Vdd on Leakage Power

4. SIMULATION AND RESULTS

In this paper, we analyze the leakage current/power of adiabatic circuits such as 2N2P, 2N2N2P. PFAL, IPGL against conventional CMOS circuit. From the analysis, we conclude that, increasing the value of Vth reduces the leakage power and also increasing the width (Wp) of pMOS transistor leads to the increase of leakage current. The leakage current can be reduced by increasing the threshold voltage of the MOS transistors. By implementing the Dual Vth design technique, the leakage current can be reduced and also the performance of the circuit will be improved to a great extent.

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