Leakage Current Reduction using Hybrid Multicarrier Modulation in a Transformerless Cascaded Multilevel Inverter for a PV System

Leakage Current Reduction using Hybrid Multicarrier Modulation in a Transformerless Cascaded Multilevel Inverter for a PV System

S. Gokulakannan 1, S. Bharanidharan 1, D. Selvakumar 1, S. Dhineshkumar 1, Mr. P. Maniraj 2

1UG Scholar, Department of EEE, M.Kumarasamy College of Engineering, Karur.

2Assistant Professor, Department of EEE, M.Kumarasamy College of Engineering, Karur

Abstract This paper proposes a hybrid multicarrier pulse width modulation (H-MCPWM) technique to leakage current reduction using hybrid multicarrier modulation in a transformerless cascaded multilevel inverter (PV) systems. The transformerless PV inverter topology has the advantage of simple structure, low weight and provides higher efficiency. However, the topology makes a path for leakage current to flow through parasitic capacitance formed between the PV module and the ground. Without adding any new component we can reduce the leakage current. By using lesser number of carrier ensures low leakage current in the transformerless PV inverter system with simplicity in implementation of the modulation technique. Experimental prototype developed in the laboratory demonstrates the performance of the proposed modulation technique in reducing the leakage current.

I.INTRODUCTION

The total power generation from the photovoltaic (PV) system is relatively small as compared to other common energy resources due to its high installation cost. Reducing the PV system cost and increasing its efficiency have attained greater research interest. One of the solutions to reduce the cost of the PV power system is to remove transformer required in the output of the PV inverter [1][3]. Most of the national electricity regulatory authority made it compulsory to use trans- former above certain threshold power in the system because it ensures galvanic isolation. However, the use of transformers increases weight, size, and cost of the PV system, and reduces the power conversion efficiency. This has motivated the research community to work in the transformerless PV system. The advancement of power electronics technology has made the use of transformerless PV inverter popular in kilo watt (kW) range by imposing standards such as DIN VDE 0126-1-1 [4], [5]. However removal of the transformer introduces harmful leakage current to flow through the parasitic capacitance which

This leakage current may increase the system losses, total harmonic distortion in the grid current, electromagnetic inferences, and safety concerns. The factors used to limit magnitude of the common mode voltage include nature of the output pulse width of the inverter, number of commutation, and grounding of the PV system [10].

The commercial transformerless centralized PV inverter has been successfully connected in roof-top projects with ratings above 10 MW and it is recognized by IEEE 1547 and other standards. This encourages the possibility to use transformer- less inverter topology for high-power applications. Next- generation PV inverter has reached higher power ratings with modularity, and redundant topologies will be adopted in the design for reliability of the inverter. Traditional two- and three- level inverters are unable to provide high efficiency and grid code requirements for higher power and voltage ratings; there- fore, converter topologies for medium-voltage and megawatt- scale PV inverters are moving toward the multilevel structures. Among various multilevel inverters, cascaded H-bridge multi- level inverter has various advantages compared to other topologies. This use of cascaded H-bridge multilevel inverter opens up the option to eliminate the transformer from the PV system. In general, following two well-established modulation techniques are available for the multilevel inverter topologies which provide constant common mode voltage: space vector modulation (SVM) and multicarrier pulse width modulation (MCPWM). The SVM technique is more constructive from the view of switching timings. The switching sequence and modulation can be decided by the users, but it requires regress effort for implementation. In, the author has demonstrated the use of SVM to reduce the leakage current in transformer- less PV inverter topology by placing zero active vectors at appropriate switching instants. However, selection of switching states is not easy for practical implementation. The MCPWM technique eliminates the problem of common mode voltage applied in the neutral clamped multilevel inverter, which in- creases the computational burden due to more number of carrier signals.

In authors have reported the effect of common mode voltage using bipolar and unipolar modulation schemes on the neutral point clamped multilevel inverter and cascaded H-bridge multilevel inverter. As the level of cascaded H-bridge multilevel inverter increases, it is expected to get reduction in leakage current, and further studies are required to know the relation between the modulation strategy and the leakage current.

Fig 1: PV-supported transformerless single-phase five-level cascaded multilevel inverter.

The cascaded H-bridge multilevel inverter has the advantages of less leakage current as compared to the conventional single H-bridge inverter due to reduced value of dc-link voltage per bridge. The common multicarrier modulation techniques used in the transformerless cascaded H-bridge multilevel PV inverter topologies introduce common mode voltage.

This letter proposes a hybrid multicarrier pulse width modulation (H-MCPWM) technique to reduce leakage current in transformerless cascaded H-bridge multilevel inverter for PV systems. When the common mode voltage changes in a large step value, it induces high leakage current in the PV system through the parasitic capacitance between the PV module and the ground. The reduced voltage transition in the common mode voltage reduces the leakage current. It is easy to implement the proposed modulation technique without much complexity and require half the number of carriers as required in the conventional MCPWM techniques.

1. CASCADED MULTILEVEL INVERTER AND HYBRID MULTICARRIER MODULATION SCHEME

   FOR CONSTANT COMMON MODE VOLTAGE

   Fig. 1 shows the PV-supported single-phase five-level cascaded H-bridge inverter topology, where two H-bridges are connected in cascade and provides a common output. The configuration of two cascaded H-bridges adds the output voltage of the upper and lower bridges to generate five-level stepped

   output voltage at the ac side, i.e., VPV , VPV /2, 0, VPV /2, and VPV . It is assumed that the grid does not contribute common mode voltage in the system [9]. The converter topology and modulation method have significant contribution in leakage current evaluation of the proposed modulation. The leakage current is produced in parasitic capacitance formed between the PV module and the ground, where common mode voltage is also induced at the same point. The mean value of voltage between outputs and a common reference point is common mode voltage gain.

   The negative terminal of dc bus is called common reference point for both upper and lower H-bridge inverter. Because of similar rating PV module both upper and lower H- bridge assumed to be same. The current flows in a capacitor is always same. The Vcm for upper full-bridge is defined as follows

   Vcm = VN + VN/2 1

   where VN and VN are the voltages between the mid-point of the upper H-bridge inverter legs to the negative terminal of the dc link, V is the voltage between the mid points of the two legs of the lower H-bridge inverter, and let Vo is the output voltage across the load. The leakage current manly depends upon the magnitude of the inverter common mode voltage. In order to derive the expression of the common mode voltage in the cascaded multilevel inverter, the following equations can be written from Fig. 1:

   Vcm + VN VL VO = 0 2

   Vcm + VN + VL – V = 0 3

   The output voltage Vo has little effect on parasitic capacitance and hence it is neglected. It is assumed that the filter inductance Ls is considered the same in the two H-bridges for simplicity of the analysis and hence the voltage drop VL due to the inductance Ls in the two H-bridges is also assumed equal [3]. The expression of the common mode voltage can be obtained in (4) by adding (2) and (3) as follows:

   2Vcm + VN + VN V = 0 4

   The common mode voltage can be expressed as follows :

   Vcm = V VN VN/2 5

   To minimize the leakage current flow through the parasitic capacitance, the common mode voltage is required to be maintained minimum during the switching instances. The minimum step value of the common mode voltage is defined by VPV /(n 1) in the MCPWM technique .

   TABLE I

   SWITCHING INSTANTS OF THE H-MCPWM TECHNIQUE FOR CONSTANT COMMON MODE VOLTAGE

   Logic conditions Switches on upper H-bridge Switches on lower H-bridge Common mode voltage

   Mode-1: (0 to T/2)	S 1 1	S 1 4	S 1 3	S 1 2	S 2 1	S 2 4	S 2 3	S 2 2	Vc m
   Vc 1 > Vr e f < Vc 2	1	1	0	0	0	0	1	1	2 VP V /4
   Vc 1 > Vr e f > Vc 2	0	1	0	1	0	0	1	1	VP V /4
   Vc 1 < Vr e f > Vc 2	0	0	1	1	0	0	1	1	2 VP V /4
   Mode-2: (T/2 to T)	S1 1	S1 4	S1 3	S1 2	S2 1	S2 4	S2 3	S2 2
   Vc 2 > Vr e f < Vc 1	1	1	0	0	0	0	1	1	2 VP V /4
   Vc 2 > Vr e f > Vc 1	1	1	0	0	1	0	1	0	VP V /4
   Vc 2 < Vr e f > Vc 1	1	1	0	0	1	1	0	0	0

   In phase disposition multicarrier pulse width modulation (PD- MCPWM), the common mode Vc m varies in the band range of ±VPV /2. However, in this modulation method, total (n1) number of carrier signals are used, where n is the inverter level. The proposed H-MCPWM is the modified version of the phase opposite disposition (POD) pulse width modulation technique, where the number of carriers required is half of that required in POD PWM and therefore computational burden is reduced. In this modulation method, the carrier signals used are in-phase with each other. The phase of all the carriers is shifted by 180° after each half- cycle. Table I shows the different switching instants and their

   corresponding magnitude of CMV. It has six switching instants, in which one instant has zero CMV, three instants have 2VPV /4, and two instants have VPV /4, CMV. There is no voltage transition in zero CMV. The CMV may take the values depending upon the inverter switch states selected since the voltage-source inverter cannot provide pure sinusoidal volt- ages and has discrete output voltage levels synthesized from the output voltage of the PV [10], [23]. The voltage transition depends upon the direction of the current in the inverter; hence, the proposed H-MCPWM modulation technique ensures the reduced common mode voltage generation in the band limit of maximum ±VPV /4. The switching pattern of the proposed H- MCPWM technique for five-level cascaded multilevel inverter is illustrated in Fig. 2. The operation of the proposed H-MCPWM is divided into two modes of operation, i.e., mode-1 and mode-2, as explained next.

   1. Mode-1 (0 to T/2)

      In this mode, all the carrier signals are in-phase with each other, the three-level voltages, i.e., 0, VPV /2, and VPV , are generated using following switching scheme:

      1. When the reference signal Vre f is smaller than the carrier signals Vc 1 and Vc 2 , then the switches S11

         , S14 , S23 , and S22 are turned ON and the complimentary switches, S13 , S12 , S21 , and S24 , are turned OFF. In this situation VN = VPV /2, V N

         = 0, and the output voltage is V =+VPV /2.

      2. When the reference signal Vre f is greater the carrier signal Vc 2 , and lesser than the carrier signal Vc 1 , then the switches S14 , S12 , S23 , and S22 are turned ON and the complimentary switches S11 , S13 ,

         S21 , and S24 are turned OFF. In this situation VN = 0, V N = 0, and the output voltage is V = 0.

         Fig. 2. Switching pattern of the proposed H-MCPWM technique for the five- level cascaded multilevel inverter.

      3. When both the carrier signals, Vc 1 and Vc2 , are smaller than the reference signal Vref , then the switches, S13 , S12 , S23 , and S22 , are turned ON and the complimentary switches, S11 , S14 , S21 , and S24 , are turned OFF. In this situation VN = 0, V N =VPV /2, and the output voltage is V = VPV /2.

   2. Mode-2 (T/2 to T)

      In this mode, all the carrier signals are phase shifted by 180°, the three-level voltages, i.e., 0, +VPV /2, and +VPV , are generated using following switching scheme.

      1. When the reference signal Vre f is smaller than the carrier signals Vc 1 and Vc 2 , then the switches, S11 , S14 , S23 , and S22 , are turned ON and the complimentary switches, S13 , S12 , S21 , and S24 , are turned OFF. In this situation V N = 0, V N =

         +VPV /2, and the output voltage is V = VPV /2.

      2. When the reference signal Vre f is greater the carrier signals Vc 1 , and lesser than the carrier signal Vc 2 ,

         the switches, S11 , S14 , S21 , and S23 , are turned ON and the complimentary switches, S13 , S12 , S22 , and S24 , are turned OFF. In this situation V N = +VPV /2, V N = +VPV /2, and the output voltage is V = 0.

      3. When both the carrier signals, Vc 1 and Vc2 , are smaller

   than the reference signal Vref , then the switches, S11 , S14 , S21 , and S24 , are turned ON and the complimentary switches, S13 , S12 , S23 , and S22 , are turned OFF. In this situation V N = VPV /2, V N = 0, and the output volt- age is V = +VPV /2.

   The summary of the switching instants employed in two modes of operation is presented in Table I. It is clearly visible from the previous discussion that the proposed H- MCPWM technique is able to generate five-level inverter output voltage and attain reduced common mode voltage in the band of maxi- mum ±VPV /4, which is superior to the conventional MCPWM technique.

2. RESULTS AND DISCUSSIONS

   To validate the proposed H-MCPWM technique, a prototype model is developed in the laboratory. The system parameters used for the experimental studies consist of four AKSHAYA ASP-1250 solar PV modules (each module is rated for 50 W), dc-link capacitance (2200 F), ground resistance (10 ), parasitic capacitance (100 nF), switching frequency (3 kHz), and inductance (5 mH). The Mitsubishi make intelligent power modules (IPM), PM50RSD120 having IGBT switches is chosen for the H-bridge inverter. The mulicarrier modulation techniques are implemented on XILINX XC3S1400A, field- programmable gate array (FPGA), which generates the gating signals for the switches of the IPM.

   Fig. 3(a)(c) shows the inverter output voltage, common mode voltage, output current and leakage current, respectively, for the PD-MCPWM, POD-MCPWM, and proposed H- MCPWM techniques, for the five-level inverter. It can be seen from the figure that the output voltages of the inverter have five voltage steps, i.e., +40 V, +20 V, 0, 20 V, and 40 V. It can be observed from Fig. 3(a) and (b), respectively, that the CMV is 35.2 V (peak) in the PD-MCPWM technique and

   26.0 V (peak) in the POD-MCPWM technique. The proposed H-MCPWM technique produces CMV of 24.5 V (peak) as ob- served from Fig. 3(c). It is in good agreement with the theoretical aspects explained in the previous section that the PD-MCPWM technique varies in the band range of ±VPV /2 and hence, further reduction of CMV is not possible due to uncontrollable switching states. The H-MCPWM offers reduced magnitude of CMV to the band limit of maximum ±VPV /4. The proposed

   Fig. 3. Inverter output voltage, common mode voltage, inverter output current, and leakage current for (a) PD-MCPWM, (b) POD-MCPWM, and (c) proposed H-MCPWM techniques.

   H-MCPWM provides reduced CMV during all the switching

   Instants; hence, it renders low leakage current flow through the

   parasitic capacitance.

   Content PD-MCPWM POD-MCPWM H-MCPWM

   Total harmonic distortion% (voltage)	30.29%	30.96%	27.41%
   Total harmonic distortion% (current)	4.71%	5.12%	4.25%
   Common mode voltage	High	Low	Low
   Leakage current (peak)	0.3 A	0.24 A	0.24 A
   Leakage current (rms)	0.098 A	0.078 A	0.070 A
   No of carrier required	4	4	2

   The simulation results comparison of different multicarrier PWM techniques, PD and POD-MCPWM [24], and the

   proposed H- MCPWM, regarding total harmonic distortion of the inverter output voltage and current, common mode voltage, leakage current magnitude and number of carrier requirements, is shown in Table II.

   Fig. 4. FPGA device utilization summary report: (a) MCPWM (both PD and POD) techniques, and (b) proposed H-MCPWM technique.

   The parameters used in simulation are: PV output voltage of

   120 V across the dc link of each H-bridge, parasitic capacitance (0.1 F), modulation index (0.9), filter inductance (1.8 mH), and load (20 ). The table clearly shows the advantage of the proposed H-MCPWM as compared to the other multicarrier PWM techniques. Also the proposed H- MCPWM has less computational burden, as compared to the conventional MCPWM. To show this, the digital processor utilization summary report for XILINX XC3S1400A FPGA is shown in Fig. 4(a) and (b), respectively, for the MCPWM (same for both PD and POD) and for the proposed H- MCPWM techniques.

3. CONCLUSION

This paper proposes a hybrid multicarrier pulse width modulation (H-MCPWM) technique to leakage current reduction using hybrid multicarrier modulation in a transformerless cascaded multilevel inverter (PV) systems. In order to reduced common mode voltage with simplicity in implementation of the modulation technique. It has been illustrated that the proposed modulation technique has less leakage current as compared to the two and three-level inverters. It is also observed that the proposed H-MCPWM offers less total harmonic distortion as compared to the conventional modulation methods. It uses only two carrier signals to generate the five-level inverter output which otherwise is four in other multicarrier modulation techniques.

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