MINIMIZATION OF HARMONICS IN INDUCTION DRIVE USING CASCADED INDUCTION DRIVE USING CASCADED

MINIMIZATION OF HARMONICS IN INDUCTION DRIVE USING CASCADED INDUCTION DRIVE USING CASCADED

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MINIMIZATION OF HARMONICS IN INDUCTION DRIVE USING CASCADED MULTILEVEL INVERTER

P.Vijayakumar1

2Research Scholar-M.E Power Electronics and Drives, Muthayammal Engineering College,

Rasipuram, Tamil Nadu, India

Abstract- In this project, a multilevel inverter was designed and implemented to operate a stand-alone solar photovoltaic system. The proposed system uses selective harmonics elimination pulse- width modulation (PWM) in the multilevel inverter to convert DC voltage from battery storage to supply AC loads. In the PWM method, the effectiveness of eliminating low-order harmonics in the inverter output voltage is studied and compared to that of the sinusoidal PWM method. This work also uses SHEPWM to predict the optimum modulation index and switching angels required for a nine-level cascaded H-bridge inverter with improved inverter output voltage. The proposed predictive method is more convincing than other techniques in providing all possible solutions with any random initial guess and for any number of levels of a multilevel inverter. The simulation results prove that the lower-order harmonics are eliminated using the optimum modulation index and switching angels. An experimental system was implemented to demonstrate the effectiveness of the proposed system.

Keywords: SHEPWM, Redundant states, Self-balancing

1. INTRODUCTION

   In recent years, environmental concerns the depletion of fossil fuel reserves have spurred significant interest in renewable energy sources. Interconnecting these intermittent sources to the utility grid on a large scale it affect the voltage/frequency control of the grid and lead to severe power quality issue. Multilevel inverter has been attracting extensive attention from as well as industry in the recent decade [1]. They have emerged as the solution too many problems related to the traditional two-level inverter. The principal advantage is to generate a good waveform quality reducing the voltage stresses on power semiconductor devices. So, they are very useful in high power ac applications. Several multilevel-PWM methods are developed for the two-level inverter and expanded to the multiple levels. The most popular are the multilevel carrier-based PWM derivatives. However, these techniques

   Dr.T.Govindaraj2

   2Prof and Head- Department of EEE, Muthayammal Engineering College,

   Rasipuram, Tamil Nadu, India

   Vijay.evergreen7@gmail.com

   offer good performances using high switching frequency [2]. The SHEPWM-based method can theoretically provide various performance advantages over all the PWM methods. These advantages include, produced the desired fundamental sinusoidal voltage while at the same time certain order harmonics are eliminated [3]. Otherwise, the use of this kind of inverter poses the dc-link capacitor unbalance problem. Two main approaches have been proposed. 1) The use of additional passive and/or active components. 2) The manipulation of the redundant switching states. The first solution causes an increase of system cost and additional power losses. For the second one, it is generally used in the space vector PWM. In fact, this paper shows that the redundant states can be associated to the selective harmonic elimination PWM in order to improve more and more the performance system in term of quality signal and power losses. In order to reduce energy loss in transmission lines and increase the overall battery capacity, the battery bank is series connected for a high-voltage dc power supply[2]-[8].

2. SELECTIVE HARMONIC ELIMINATION

   This is also termed as the optimized PWM technique. By reversing the phase voltages a few times during each half cycle, it is possible to eliminate lower order harmonics selectively. However, the higher order harmonics may increase in magnitudes, but the current harmonics are not significantly affected due to low pass filter characteristics of the AC system. The voltage reversals are affected at chosen instants such that the notches (caused by the voltage reversals) are placed symmetrically about the centre line of each half cycle. If there are p switching (voltage reversals)

   in a quarter cycle, the rms value of the nth harmonic voltage is given by,

   (1)

   Where are switching angles within each quarter cycle. There are p degrees of freedom and are used to cancel (p-1) harmonic components in the voltage

   and control the fundamental voltage. For example, if there are 3 switching at , we can eliminate the fifth and seventh harmonics in addition to control the fundamental voltage. We get 3 transcendental equations is given by,

   (2)

   (3)

   (4)

   Note that although the phase voltage contains triple harmonics, the line to line voltages are free from them [7]-[8].

   with multiple switch states. The last one is the vector zero with five different switch states. They have any effect on the DC- link voltages. So, only the second group will be used to ensure the capacitor voltages balance. Different switch states force load current to flow through different paths. Thus the direction of current through the DC-link capacitors is different and variation of capacitor voltages is minimizing the difference between the voltages of the four capacitors by selecting the suitable redundancy among the different. We express the capacitor currents by the two ac load current ia and ib .

3. CIRCUIT DIAGRAM

   3(A) Operation of Circuit Diagram

   Fig 1 Circuit Diagram

   According to their sign, we can know the effect of each state on the capacitor behavior (charge or discharge).

   In order to keep the four voltages equal, we will make use of the switch states of the 9-level inverter. Three groups are distinguished from 125 switch states. The first one is formed by 24 vectors which do not connect any of the phases to the common capacitors potential and so the capacitor voltages remains unaffected. The second group has 36 vectors

   voltage vectors of group 2. The switch state selected has to unload the most loaded capacitor voltage and load the unloaded one. Therefore, capacitor voltage derivations have to be considered. Substitute the modulation 1 1 4 by the first redundancy (0 0 3) which allows charging C1 and discharging C4. In the contrariwise, we let the initial state. The same

   operation is done using the PWM signal given by the SHE technique at the end; we obtain another leg voltage waveform which provides the same modulation voltage waveform and the same harmonics spectrum. The proposed capacitor balancing method has been assessed by simulation.

4. SIMULATION CIRCUIT DIAGRAM

Fig 2 Simulation circuit for 9-level Cascaded Inverter

4 (A) Simulation Results

The proposed nine-level inverter circuit has been tested on a 230V, 50Hz, induction motor drive with V/f control scheme at a switching frequency of 1 kHz. This simulation diagram is drawn in MATLAB Software package. In this diagram, MOSFET Switches are connected in structure of cascaded with H-bridge. SHEPWM technique is used in this project for controlling the inverter by giving gate pulse to MOSFET Switches. The inverter dc-link voltage is set to 230

V. The hysteresis limit for the capacitor is set at 5% of the respective capacitor voltage. The capacitors are sized suitably so that the voltage of the capacitors would not cross the hysteresis limit in two switching cycles at full load current. Simulation circuit for nine-level in switching angles is calculated by give the firing pulses to te nine level inverter, the staircase voltage waveform is obtained. The FFT analysis is done in both the cases. The THD calculated in case of resistive load is 14.49% while in case of RL load is further reduced to 3.08%. The calculation revealed that 3rd, 5th and 7th harmonics is significantly reduced up to four decimal places and thus overall THD% is reduced. A full-bridge inverter or so-called H-bridge cell is introduced. Basically, an H bridge cell can generate up to three output voltage levels. The appropriate gate control signal and blinking time are presented. Multilevel inverter using cascaded-inverter with SDCSs is introduced in both single-phase and three-phase structure. The output voltage is the sum of the output voltage of each H-bridge cell. In three-phase system, the voltage THD can be improved in line voltage. Finally, the reason to use

SDCSs is explained the concept of the optimized harmonic stepped-waveform technique will be presented.

1. output voltage waveform

   Fig.4.1 Output Voltage Waveform

2. output current waveform

   Fig.4.2. Output Current Waveform

3. filtered output voltage

   Fig.4.3. Filtered Output Voltage Waveform

4. the analysis of output voltage

Fig.4.4. THD Analysis of Output Voltage

ent in D

to

el

In this project, modulation index is 0.8 is used in pulse generator. The gate pulses are given to inverter through the subsystem. From subsystem the pulses are given to Goto and then Goto are linked with from blocks then pulses given to switches. Then output current and output voltage is determined from the simulation results. The single phase induction motor is connected in this circuit The THD analysis of output curr and output voltage are determined by the simulation. The ma advantages of this project are harmonics reduction. The TH percentage of the output voltage is 3.34%. When compare other topology it has better harmonic reduction properties

. 5. CONCLUSION

Both optimization of switching angles of nine-lev output waveform using SHEPWM and DC-link voltages balance are investigated in this study. The programmed PWM allows eliminating harmonics row 5, 7 and 9th orders with a good control of the fundamental voltage. In order to keep as well as possible the four capacitor voltages equal, we have made use the 61 switch states of the nine-level inverter. Its matrix representation simplify the redundant states analyse. The obtained results show the DC-link balancing while maintaining the SHEPWM performances.

6. REFERENCES

1. Chung-Ming Young, Neng-Yi Chu, Neng-Yi Chu, Liang-Rui Chen, Yu- Chih Hsiao, & Chia-Zer Li, A Single phase multilevel inverter with Battery Balancing,IEEE Transactions on Industrial Electronics, Vol 60, No 5 May 2013.

2. B. Y. Chen and Y. S. Lai, New digital-controlled technique for battery charger with constant current and voltage control without current feedback , IEEE Transactions on Industrial Electronics, Vol. 59, no. 3, pp. 15451553, Mar. 2012.

3. Pablo Lezana, Jose Rodriguez, and Diego A. Oyarzun, Cascaded Multilevel Inverter With Regeneration Capability and Reduced Number of Switches , IEEE Transactions on Industrial Electronics, Vol. 55, NO. 3, Mar. 2008.

4. Leon M. Tolbert, Burak Ozpineci, and John N. Chiasson, A Five-Level Three-Phase Hybrid Cascade Multilevel Inverter Using a Single DC Source for a PM Synchronous Motor Drive, IEEE Applied Power Electronics Conference, APEC 2007.

5. R.Narmatha and T.Govindaraj, Inverter Dead-Time Elimination for Reducing Harmonic Distortion and Improving Power Quality, International Journal of

   Asian Scientific Research, Vol.3, April 2013.

6. Dr.T.Govindaraj, and T.Srinivasan, An Hybrid Five-Level Inverter Topology with Single-DC Supply fed Special Electric Drive, International Journal of Advanced and Innovative Research ISSN: 2278-7844, Dec- 2012,pp 542-548

7. K.R.Padiyar, , HVDC Power Transmission Systems, New Age International (P) Ltd., New Delhi, 2002.

8. Rashid M.H., Power Electronics Circuits, Devices and Applications ", Prentice Hall India, Third Edition, New Delhi, 2004.

P.Vijayakumar born in Erode, India, 1991. He received the B.E degree from Sengunthar Engineering college, Tiruchengode, 2012. Now he pursuing M.E degree in Muthayammal Engineering College, Rasipuram, India. His area of intrest in power Electronics,Electric drives and control.

Dr.Govindaraj Thangavel born in Tiruppur , India in1964. He received the B.E. degree from CoimbatoreInstitute of Technology, M.E. degree from PSG College of Technology and Ph.D. from Jadavpur University, Kolkatta,India in1987, 1993 and 2010 respectively. His Biography is included in Who's Who in Science and Engineering 2011 2012 (11th Edition).Scientific Award of

Excellence 2011 from American Biographical Institute (ABI). Outstandin Scientist ofthe 21st century by International Biographical centreof Cambridge, England 2011. Since July 2009 he has been Professor and Head of the Department of Electrical and Electronics Engineering, Muthayammal Engineering College affiliated to Anna University, Chennai, India. His Current research interests includes Permanent magnet machines, Axial flux Linear oscillating Motor, Advanced Embedded power electronics controllers,finite element analysis of special electrical machines,Power system Engineering and Intelligent controllers.He is a Fellow of Institution of Engineers India(FIE) and Chartered Engineer (India).Senior Member of International Association of Computer Science and Information. Technology (IACSIT). Member of International Association of Engineers(IAENG), Life Member of Indian Society forTechnical Education(MISTE). Ph.D. Recognized Research Supervisor for Anna University and Satyabama University Chennai. Editorial Board Member for journals like International Journal of Computer and Electrical Engineering,International Journal of Engineering and

Technology,International Journal of Engineering and Advanced Technology (IJEAT).International Journal Peer Reviewer for Taylor &Francis International Journal Electrical Power Components & SystemUnited Kingdom, Journal of Electrical and Electronics Engineering Research, Journal of Engineering and Technology Research (JETR),International Journal of the Physical Sciences,Association for the Advancement of Modelling and Simulation Techniques in Enterprises, International Journal of Engineering & Computer Science (IJECS),Scientific Research and Essays,Journal of Engineering and Computer Innovation,E3 Journal of Energy Oil and Gas Research,World Academy of Science, Engineering and Technology, Journal of Electrical and Control Engineering(JECE),Applied Computational Electromagnetics Society etc.. He has published 132 research papers in International/National Conferences and Journals. Organized 40 National International Conferences/Seminars/Workshops. Received Best paper awardfor ICEESPEEE 09 conference paper. Coordinator for AICTE Sponsored SDP on special Drives,2011.Coordinator for AICTE Sponsored National Seminar on Computational Intelligence Techniques in Green Energy, 2011.Chief Coordinator and Investigator for AICTE sponsored MODROBS-Modernization of Electrical Machines Laboratory. Coordinator for AICTE Sponsored International Seminar on Power Quality Issues in Renewable Energy Sources and Hybrid Generating System, July 2013.