Multiple Single Input Change Test Vectors and Its Application Over Built In Self Testing

Multiple Single Input Change Test Vectors and Its Application Over Built In Self Testing

Nikhitha Jose

PG Scholar Depatment of ECE Akshaya College of Engineering and Technology,Coimatore

Shincy C. V

PG Scholar Department of ECE Akshaya College of Engineering and Technology,Coimbatore

Preethi. R

PG Scholar Depaartment of ECE Akshaya College of Engineering and Technology,Coimbatore

Gladwin Moses Stephen

Assistant Professor Department of ECE Akshaya College of Engineering and Technology,Coimbatore

Abstract

This concept gives the generation of well advanced test pattern generation (TPG) for the built in self test techniques. This method generates multiple single input change (MSIC) vectors, so that each vector to the scan chains is of a single input change (SIC) ,thus when there are multiple scan chains, there occurs the generation of MSIC vectors. For the MSIC vector generation, the use of the devices such as the Reconfigurable Johnsons Counter and Scalable SIC Counter is being used. As a result, the sequences of minimum transitions have been obtained. Both the test per clock and test per scan are flexible to the Scalable SIC Counter for the vector generation. This method save the test power and give a better fault coverage without an increase in the test length. The analysis results in a low input transition and uniform pattern distribution.

Scan Chain1

Scan Chain m

Keywords: Built In Self Test (BIST), Single Input Change (SIC), Test Pattern Generator (TPG), Low Power.

1. Minimum transition: The vectors are of SIC to each scan chain to minimize the transition also to minimize the transition and also to lower the test power.

2. Uniform pattern distribution: The test patterns are distributed uniformly to each and every scan chains at every clock.

3. Pattern uniqueness: No vectors are being repeated.

4. Low hardware by extra TPGS: The hardware to implement the TPGs are very low.

2. Proposed MSIC-TPG

This is the TPG of converting a SIC vector of low transition for a number of scan chains in a unique manner, a SIC generates, a clock and a control block.

Jm+sm-1 Jm-3+sm-1 Jm-1+sm-1

J1+s0 Jl-2+s0 J0+s0

J2+s1 Jl-1+s1 J1+s0

.

1. Introduction

   PIs of the CUT

   The circuit under test (CUT) is introduced with an on chip test hardware to give the BIST to reduce the complexity in VLSI testing. It uses the principle of linear feedback shift register (LFSR). The CUT suffers from high switching activity due to the pseudorandom test pattern generated by the LFSR. This also leads to power loss. The LFSR is also required to produce long pseudorandom sequences to have high fault coverage.

   Scan Chain2

   S0 s1.sm-1

   .

   There is a chance of damaging the circuit and decrease the product yield and life time.

   The switching activity during each shift from one scan cell to another is being decreased. The paper has got the following merits

   Figure 1. Symbolic representation of MSIC Patterns

   1. MSIC Vector Generation Through Reconfigurable Johnsons Counter and Scalable SIC Counter

      The given work mainly consists of a test pattern generation method given by a Reconfigurable Johnson Counter. The following methods are the way to generate the test vectors in a Reconfigurable Johnsons Counter:

      1. Initialization

      2. Circular shift register

      3. Normal mode

         1. Method of Test Pattern Generation

            Consider there are m primary inputs (PIs) and

            M scan chain has l scan cells. The vectors S(t)=S0(t)S1(t)S2(t)Sm-1(t) are the ones generated by an m-bit LFSR. Here, the bit of LFSR is known to be a seed. The Johnson Counter releases get XORed with S=S0 S1 S2.SM-1 and the result is X1Xl

            +1X2l+1.X(M-1)l+1 gets shifted to the chains. During 2nd clock cycle, J=J0J1J2..Jl-1 is circularly shifted in the form of J=Jl-1 J0 J1 J2 ..Jl-2, again XORed with S=S0S1S2SM-1. The resultant vectors X2xl+2 X2l+2..X(M-1)l+2 is shifted to M scan chains. The chains are loaded after l clocks in a unique way. Since the Reconfigurable Johnsons Counter can generate the codewords through the circular shift, the counter is circular Johnson Counter is called as a linear sequential decompressor.

         2. Reconfigurable Johnson Counter

            For smaller scan length, a Reconfigurable Johnson Counter is developed to generate a SIC sequence in the time domain. It is SIC Generator with three operation modes:

            1. Initialization mode: When RJ mode= 1 and Init=0, the counter will be initialized to all zero states by clocking CLK2 more than 1 times.

            2. Circular shift register mode: When RJ=Init=1, each stage of the Johnson Counter will output a Johnson codeword by clocking CLK2 1 time.

            3. Normal mode: RJ mode=0, the Reconfigurable Johnson Counter will generate 2l unique SIC vectors by clocking CLK2 2l times.

         3.2.1. Limitations. The above work has an ability to do the testing of a small range of circuits. The large test bit range is generated by the scalable

         SIC Counter. It has also the merit of overcoming the delay of testing.

         Figure 2. SIC Generators. a. Reconfigurable Johnson Counter

         1. Scalable SIC Counter

            When the scan chain number M is smaller than scan chain length l, a counter known as the Scalable SIC Counter is being developed. It consists of a k-bit adder and a subtractor with a clocking SE signal, and a k-bit subtractor with a clocking SE signal along with a shift register, both clocked by CLK2. Also contains k multiplexers. The SE signals enables the k-bit adder to generate the number of 1s (0s) towards the shift register to be filled. The output waveform of the counter is to be shown in the simulated result. The three operation modes are shown below:

            1. If SE=0, the adder count is stored to the subtractor. But when SE=1, the k-bit subtractor contents reduces to all zeros gradually.

            2. When SE=1, the subtractor contents are decreased, but not to all zeros.

            3. The needed 1s and 0s are shifted to the register by clocking CLK2l times and the unique codewords are applied to the chains.

         The full design, ISCAS89S13 with scan length as 64. 6 D-flip flops are meant each for the adder as well as the subtractor, 10 for a 10- bit shift register meant for the 10 scan chains,

         19 combinational logic gate along with 6 multiplexers to build the Scalable SIC Counter. In total, there are 204 gates. To implement a 64-bit Johnson Counter, it requires the 64 D- flip flops of 428 gates. The MSIC-TPG overhead is reduced by a Scalable SIC Counter.

         Figure 2. b. Scalable SIC Counter

   2. MSIC TPG for Test pet clock

      The inputs of the XOR gate tapped from a seed generator and Johnson Counter outputs. The XOR gate output is fed into the PIs of CUT. The testing undergoes the following methods:

      1. When a clock is given for one time from the CLK1, the seed generator generates a new seed.

      2. Similarly the Johnson Counter also generates a new vector by a clock CLK2.

      3. Repeating the above step until a 2l number of Johnson vectors are produced.

      4. Repeat for an expected fault coverage.

         Figure 3. MSIC-TPGs for test per clock.

   3. MSIC-TPG For Test per Scan

      The XOR gate input is from the see generator and also from the SIC Counter and their output are Given below is the test procedure:

      1. A new seed is generated by the seed generator.

      2. When RJ mode is 0, then the Johnson Counter will operate in a normal mode to generate the vector by giving a clock CLK2.

      3. After that, both the RJ mode and the Init is set to 1, so that a circular shift register mode is being activated for producing l codewords by clocking CLK2 l times.

      4. Repeat for 2l vector generation for an expected fault coverage.

         Figure 4. MSIC-TPGs for test per scan

   4. MSIC Sequences Properties

      1. Reduction in Switching Activity

         M unique sequences are applied to the M PIs of CUT in the test per clock. Where as in the test per scan, the CUTs PIs are kept unchanged during the shifting and for each transition, the codewords are not greater than 2. A higher reduction ratios are shown when the methods given in the references [] and [] have been compared.

      2. MSIC Pattern Uniform Distribution

         The repetition of the input patterns indicates the non-uniformity. It can result in low fault coverage if there is an absence of the patterns which is only capable of detecting the particular fault coverage. Uniformity is meant for high fault coverage. The initial seed has less impact on this kind of uniform distribution.

      3. Test Length and Fault Coverage Relationship

      Initial test vector is related to the test length of a conventional LFSR. To achieve a full fault coverage, it depends upon the initial vector in conventional LFSR TPGs. The fault model available is a stuck at fault model. There are two types of LFSR sequences such as the best case and the worst case LFSR sequences. The growth rate of

      fault coverage with the MSIC sequence is close to that with the LFSR in the best case. The uniform distribution of MSIC pattern alleviates the depending relationship between the TPGs initial state and the test patterns.

   5. Simulation Result

      Figure 5. a. Simulation result of Reconfigurable Johnson Counter.

      Figure 5. b. Simulation result of Scalable SIC Counter.

   6. Result Analysis

      The comparison of the estimated power of a 4- bit LFSR is done with that of the 4-bit Reconfigurable Johnson Counter. In the same way, a 6-bit LFSR is being compared with a 6-bit Scalable SIC Counter on the basis of its power and thermal energy. The table representing the above mentioned concept is showed below.

      	4-bit LFSR	4-bit 6-bit LFSR Reconfigurable Johnson Counter	6-bit Scalable SIC Counter
      Total Estimated Power (mW)	113	107 234	208
      Estimated Juncction Temperature (0C)	27	27 29	28
      Ambicat Temperature (0C)	25	25 25	25
      Case Temperature (0C)	27	27 28	28

      Table 1. Result Comparison

   7. Conclusion

      This paper is based on a low power test pattern generation that is implemented easily by the hardware. The results showed that the MSIC had the uniform distribution, low input transition density. A flexible test per scan and test per clock schemes can be developed with the combinations of Reconfigurable Johnson and Scalable SIC Counters.

      In future work, the seed generator is being replaced by the CMOS Parallel Counter. It works under the principle of a look ahead logic. In a look ahead logic, there occurs a generation of the partial product in the TPG. As a result, there is maximum time conversation and no delay for the switching activity.

   8. References

1. Bing Liang, Feng Liang, Gunche Zhang and Shaochong Lei, Test Patterns of Multiple SIC Vectors: Theory and Application in BIST Schemes , 2013.

2. P. Girard,Survey of low power testing of VLSI circuits, vol.19,no.3,pp. 80-90,May-Jun.2002.

3. S. Chun, T. Kim and S. Kang, A new low energy BIST, in Proc. 11th Int. Symp. Qual. Electron. Design. Apr. 2010, pp. 689-696.

4. S. Chun, T. Kim and S. Kang, A new low energy BIST using a satistical code, in Proc. Asia South Pacific Design Autom. Conf. , Mar 2008, pp.647-652.

5. Wanderlich and Gerstendorfer, Low power built in self test, in Proc. Eur. Test Workshop, 1998, pp. 49-53.

6. X. Zhang, K. Roy and S. Bhaumik, POWERTEST: A tool for energy conscious weighted random pattern testing," in Proc. 12th Int. Conf. VLSI Design, Jan. 1999, pp. 416-422.

7. Y. Zorian, A distributed BIST control scheme for complex VLSI circuits, IEEE Design Test Comput. , vol. 19 no.3, pp. 80-90, May-Jun. 2002.

8. Zhou, Y. Z. Ye, Z Li Wu and R. Ke, A new low power test pattern generator using a variable length ring counter, in Proc. Qual. Electron. Design, Mar. 2009, pp. 248-252.