New PFC design using Multiple Buck Converters

New PFC design using Multiple Buck Converters

Doaa S. Mohammed

Computer Engineering Department, Al-Rasheed University College Baghdad, Iraq

AbstractThis paper presents a new design of a power factor correction (PFC) technique with a step down dc-dc buck converter. This research proposes PFC that adopts voltage- controlled parallel-connected buck converters. The parallel connection structure increases the power level, enhances the overall efficiency and power system reliability. However, unequally current distribution between converters is a major problem which may lead to inductor saturation and even destroy the converters which handles the larger current. For this reason, a suitable control scheme used to overcome this issue.

A suitable control scheme is suggested for the parallel connected buck converters. An average control scheme is suggested for the PFC system. In this scheme, the output current of each converter tracks the average load current which is the ratio of the load current to the number of parallel-connected converters. This scheme is a modular but needs only one information which is the number of parallel-connected converters to be shared between converters. A mathematical analysis is performed to examine the system performances including current distribution between the parallel-connected converters and stability of proposed PFC. The analysis reflects the system stability and shows the possibility of maintaining even current distribution between the converters. A Simulation results show the excellent performance of the PFC with an equally current distribution between converters.

KeywordsPFC; buck; dc-dc converter; ac-dc; pwm.

1. INTRODUCTION

   Electrical power converters is a very important part of industry. Ac-dc converters (rectifiers) are used as a major part for switched mode power supplies, uninterrupted power supplies (UPS), battery chargers [1]. For these reasons, ac-dc converters have attracted a great deal of attention and several commercial ac-dc converters have been developed. A main problem with ac-dc converters is a power factor (PF). Besides power losses, PF causes harmonics that travel down the neutral line and disrupt other devices connected to the AC mains line. This reason has prompted researchers to develop several custom versions and a lot of researches have been carried out to design and implement PFC.

   One scheme of PFC that suggested to use dc-dc converter (like buck, boost, Fly back,..,etc.) as a PFC, is placed after the rectifier stage and before the output storage capacitor [2,3,4]. In general, PFC can be either a passive PFC or active PFC. A simple way to enhance power factor of the rectifiers is by adding a passive filter after it. These passive filters could be built from capacitors and inductors. Although the passive filters is simple in design and control, but it suffering from the high inductors current and high capacitors voltage. Also a passive filter has a bulky sizes of capacitors and inductors [5, 6]. An active PFC built on a switching electronic devices like, MOSFETs, IGBTs.

   A conventional step-down buck converter is shown in Fig. 1, it regulates an input voltage to give an output voltage smaller than input.

   Fig. 1. Dc-dc buck converter.

   This research present a modular PFC built on paralleled voltage control buck converters. This feature will enhance the reliability and overall system efficiency. Furthermore, the ripple of the output current and voltage will be decrease [7].

2. PROPOSED PFC

   1. Main circuit

      A proposed PFC with multiple dc-dc converters is shown in Fig. 2. Where two voltage controlled step down buck dc-dc converters are supplied from same source (output of the rectifier) and connected in same output. A main problem with the parallel connection of dc-dc converters is unequally current distribution between converters which may lead to inductor saturation and even destroy the converters which handles the larger current. To avoid this problem a duty cycle of the two converters (Dm) is modified. In basic words, a total output current from the paralleled converters is sensed and divided by 2 (2 is the number of the converters that connected in parallel). This new current are compare with each individual converter current to give a new duty cycle (Dnew) that add to the main duty cycle to give a modified duty cycle

      (D) that equal in two converters to share equal current in each converter.

      Fig. 2. A proposed PFC with multiple dc-dc converters.

   2. Mathematical analysis

   The schematic diagram of the conventional buck converter is shown in Fig. 1 and the jth modeling for the closed loop

   voltage control is shown in Fig. 3. A switching voltage drop could be represent as Vsw in the modelling [8]. And it's a main effect of the unequally sharing current between converters.

   A new closed loop transfer function will be:

   Then, the output voltage will be:

   (6)

   Fig. 3. jth modeling for the closed loop voltage control.

   From fig. 3 above the closed loop transfer functions could be written as below:

   The output current will be as below:

   To find current that circulated between converters,

3. SIMULATION RESULTS

   1. Parallel operation

      (7)

      (8)

      And

      So, the output voltage equation could be arrange to be:

      (1)

      Where Gc is a transfer function of PI controller, and it equal to:

      From (1) the output current could be written as below:

      (2)

      So, the converters individual currents will be:

      That lead to average current that between converters will be:

      (3)

      To find current that circulated between converters, sub. (3) from (2) :

      To validate that an equal current share in the both buck converter according to our design, a Simulink model for only two paralleled buck converters is built in a MATLAB Simulink program. Fig. 5 shows the waveforms of the output currents for the two paralleled buck converters with the total load current, when the load equal to 15. It clear that the suggested sharing control method is excellent in control by make the two converters have a same value. Fig. 6 shows the waveforms of the output currents for the two paralleled buck converters with the total load current, when the load equal to 150. It also shows that the suggested sharing control method is excellent in control by make the two converters have a same value. Then, when the load resistance equal to 300, the suggested control method work excellent and the currents waveforms that shown in the Fig. 7. From the results above, our current sharing control method was work very good and give an excellent sharing among the two buck converters.

      The converters are connected in parallel, so: Then (4) could be written as:

      (4)

      (5)

      (6)

      When the two converters are connected in parallel, the model of the buck converters will be as shown in Fig. 4.

      Fig. 4. Buck converter model for the Proposed PFC.

      Fig. 5. Waveforms of the output converters currents at 15.

      Fig. 6. Waveforms of the output converters currents at 150.

      Fig. 7. Waveforms of the output converters currents at 300.

   2. Proposed PFC simulation results

   After successful parallel operation simulation tests of the power stage of the PFC. In order to validate designed PFC, a simulation made by using MATLAB Simulink program. Fig. 8 shows a steady state waveforms of the input voltage and current at full load operation (750w). The waveforms are sinusoidal and the total harmonic distortion (THD) is about 3% nd the input power factor 0.999. Fig. 9 shows the input waveforms at load equal to 200w, and it's clear that the THD is about 10% and the input power factor equal to 0.990. With different loads a PF is calculated and write down before and after using our suggested PFC and the comparison result is shown in the Fig. 10.

   Fig. 8. Inputs voltage and current waveforms at load equal 750w.

   Fig. 9. Inputs voltage and current waveforms at load equal 200w.

   Fig. 10. A calculated PF before and after using our suggested PFC.

4. CONCLUSION

A new design of PFC is discussed through this paper by using a multiple step down buck converters that connected in parallel. At the first, a main problem of unequally current sharing between the converters is analysis and solved mathematically and by simulation. A simulation results gave us an excellent behavior to go ahead to apply our design to the rectifier. Then, an overall power system with suggested PFC and rectifier are built in a Mat lab Simulink. A simulation results show a good power factor correction compared with the power factor of the system without PFC connected as that shown in the Fig. 10. A good idea for future work is to prove that the design of parallel operation is modular by connect more than two buck converters in parallel.

REFERENCES

1. H.Z.Azazi, E. E. EL-Kholy, S.A.Mahmoud and S.S.Shokralla, Review of Passive and Active Circuits for Power Factor Correction in Single Phase, Low Power AC-DC Converters, International Middle East Power Systems Conference (MEPCON10),Cairo University, Egypt, December 19-21, 2010.

2. D. S. Chen and J.-S. Lai, A Study of Power Correction Boost Converteroperating at CCM-DCM Mode, in Proc. IEEE Southeastcon, vol. 93, pp. 6-13, 1993.

3. V. Grigore and J. Kyyra, High Power Factor Rectifier Based on Buck Converter Operating in Discontinuous Capacitor Voltage Mode, in Proc. IEEE Appl. Power Electron. Conf. Expo., Mar. 1999, pp. 612-618.

4. W. Tang, Y. Jiang, G. C. Hua, F. C. Lee and I. Cohen, Power Factor Correction with Fly back Converter Em-ploying Charge Control in APEC93 Rec., pp. 293-298.

5. N. Mohan, T. M. Undeland, W. P. Robbins, "Power Electronics: Converters, Applications, and Design," New York, NY, USA, John Wiley & Sons, Inc., 1995.

6. Supratim Basu, "Single Phase Active Power Factor Correction Converters Methods for Optimizing EMI, Performance and Costs," PhD. Thesis, Chalmers University of Technology, Göteborg, Sweden, June 2006.

7. L. de la Torre, "High Frequency High Efficiency DC/DC- Converters," in Proceedings of the 1995 European Conference on Power Electronics and Application, Seville, pp.2.106-2.110.

8. Y. Zhang, S. Duan, Y. Kang, and J. Chen, "The Restrain of Harmonic Circulating Currents between Parallel Inverters," 5th International Power Electronics and Motion Control Conference, pp. 1-5, 2006.