Performance Evaluation Of Strained Si/Sige N-Channel Mosfet

Performance Evaluation Of Strained Si/Sige N-Channel Mosfet

1 Rakhi Sharma, 2 Ajay Kumar Yadav, 3 Dr.D.B.Ojha, 4Vishal Upmanu

Mewar University, Chittorgarh (Raj.)

ABSTRACT

Electronics, and in particular the integrated circuit has made possible the design of powerful and flexible processors which provide highly intelligent and adaptable devices for the user. Integrated circuit memories fabricated by using MOS (Metal-Oxide-Semiconductor) technology have provided the essential elements to complement these processors and, together with a wide range of logic and analog integrated circuitry. N MOS technology has an important role in IC fabrication. Works are going on to improve the performance of n MOSFETs. Device scaling which was a major driving force in the development of high density ICs is facing a number of obstacles, making it very difficult to sustain the trend of device performance improvements. Consequently, innovative device structures and materials are actively being investigated to boost performance. The tensile-strained-Si MOSFET is getting attention recently, as it significantly enhances the inversion layer electron mobility and hence the performance of deep submicron MOSFETs for high speed operations. One of the suggestions from researcher was to develop a strained SiGe channel structure grown on a normal Si substrate. These SiGe-channel MOSFETs show some significantly better electrical characteristics as compared to the silicon- channel MOSFETs. In this performance of a strained Si/SiGe n-Channel MOSFET has been studied on the basis of ORCAD simulations. Parameters needed for the simulations were first obtained on the basis of analytical model. Physics based 2-D model for the surface potential variation along the channel in an n-channel SiGe MOSFETs is developed by solving the two- dimensional Poissons equation. It is simple in its

functional form and lends itself to efficient computation. Concept of strained silicon and effects due to germanium concentration in device parameters are also studied in this work Strained Si/SiGe n-channel MOSFET has tremendous applications in biomedical field. The modern communication world is also taking interest to use strained Si/SiGe n-channel MOSFET in its applications because of high speed of operation

INTRODUCTION

Electronics is characterized by reliability, low power dissipation, extremely low weight and volume, and low cost, coupled with an ability to cope easily with a high degree of sophistication and complexity. Electronics, and in particular the integrated circuit has made possible the design of powerful and flexible processors which provide highly intelligent and adaptable devices for the user. Integrated circuit memories fabricated by using MOS (Metal-Oxide- Semiconductor) technology have provided the essential elements to complement these processors and, together with a wide range of logic and analog integrated circuitry. Within the bounds of MOS technology the possible circuit realizations may be based on p- MOS, n-MOS and BiCMOS devices. Although CMOS is the dominant technology, but emphasis is given to nMOS technology. The reasons for this are as follows slightly less than the dielectric constant r of the substrate because the fringing fields from the patch to the ground plane are not confined in the dielectric only, but are also spread in the air.

If the design of nMOS technology is to be carried out effectively or the performance of circuits based on it is to be understood than one must have a sound knowledge of MOS active device. For the performance improvement of n- MOS device, since last 3 decades scaling has been the primary means. However, device scaling is facing a number of obstacles, making it very difficult to sustain the trend of device performance improvements. Consequently, innovative device structures and materials are actively being investigated to boost performance [1], [2]. The tensile-strained-Si MOSFET is getting attention recently, as it significantly enhances the inversion layer electron mobility and hence the performance of deep submicron MOSFETs for high speed operations. One of the suggestions from researcher was to develop a strained SiGe channel structure grown on a normal Si substrate [3], [4]. A SiGe layer of several nm thick provides the big advantage that only a small change from the standard fabrication process is needed for electron mobility enhancement. High-speed devices require a large charging current that is now obtained by increasing their carrier mobility with the introduction of SiGe layer.

CONCEPT OF STRAINED SILICON

The tensile-strained-Si MOSFET is getting attention recently, as it significantly enhances the inversion layer electron mobility and hence the performance of deep submicron MOSFETs. The strained-Si MOSFETs exhibit a shifted threshold voltage from conventional Si devices, due to the band offset at the heterojunction between the strained-Si and SiGe layers. The strain of Si is obtained from a Si layer grown epitaxially on a relaxed Si Ge layer. A chemical mechanical polishing (CMP) step is introduced in the middle of SiGe epitaxy to reduce the surface roughness. Overall thermal budget and etch steps can be controlled tightly to minimize strain relaxation, Ge out-diffusion, and strained-Si consumption [37]. Relaxed Si1-xGex graded buffers can be used

currents. Figure shows the impact of Ge in the lattice of silicon when SiGe layer is formed.

Figure : (a) Ge is introduced into the lattice (b) Si is deposited on top of the SiGe. Atoms align causing a strain in the lattice.

ANALYSIS AND DESIGN

MATHEMATICAL FORMULATION FOR SURFACE POTENTIAL

As (x, y) i (x, y) i (x) is defined as the intrinsic potential at a point x, y

with respect to the intrinsic potential of the p-type substrate [46].The substrate is assumed to be uniformly doped with a concentration Na .

In the oxide region AFGH, Poissons equation becomes a homogeneous (Laplace) equation,

as a template for epitaxially growing Si in a state of biaxial tensile strain and n-type MOSFETs

fabricated on strained-silicon Si

demonstrate higher effective mobility than those on Czochralski-grown Si (Cz-Si) [49]. Even in

2

x 2 +

2

y 2

= 0 (1)

devices with high channel doping and short gate lengths, the strain-induced electron mobility enhancement leads directly to increased drive

In the depletion region in silicon, the concentrations of both types of mobile carriers are negligible under subthreshold conditions.

Therefore, in ABEF, Poissins equation is approximated by-

Where Vg

and

Vds

are the gate and

source-drain voltages.

V fb

is the flat-band

2

x 2

2

+

y 2

qN a

=

SiGe

(2)

voltage of the gate electrode, and bi is the built- in potential of the source- or drain-to-substrate junction. For an abrupt n+-p junction, bi Eg / 2q B ,

The length of the SiGe region is equal to the

KT Na

where B ln .

channel length L. the depth is given by the depletion layer width,Wd , to be determined later.As the normal component of the electric field

q Ni

The bottom boundary is movable one, as Wd

will

changes by a factor of

SiGe / ox 3

across

change with the gate voltageVg . The distance BC

the silicon-oxide boundary AF [46]. To eliminate this boundary condition so that and its

derivatives are continuous, the oxide is replaced by an equivalet region of the same dielectric

is approximately given by the source junction depletion width,

constant as SiGe, but with the thickness equal

to3 tox . This preserves the capacitance and allows the entire rectangular region to be treated as a homogeneous material of dielectric

Ws =

2 si Ge bi

qN a

(6)

constant SiGe . The drawback is that it may cause

some error in tangential field, whose magnitude

Similarly, DE is given by the drain junction depletion width,

does not change across the silicon-oxide boundary.

In the equivalent structure, the tangential field apparently experiences a thicker-than-actual oxide. The errors are expected to be smaller when the gate oxide is thin compared to the silicon

WD

2 si Ge ( bi Vds )

qNa

(7)

depletion depth Wd so that the oxide field is dominated by its normal component.

If the source and drain junctions are abrupt and deeper thanWd , the set of simplified boundary conditions will be as follows:

(3tox , y)Vg V fb

The boundary conditions along FG and HA are assumed to very linearly between the end point values, while those along BC and BE are assumed to vary parabolically between the end points.The surface potential solution technique makes use of the superposition principle and breaks the electrostatic potential into the following terms.Here v(x, y) is a solution to the

along GH.

inhomogen(e4o.3us) (Poissons) equation and satisfies the top boundary condition, Equation .

(x,0) bi along AB.		(3)
(x,L) bi along EF.	(4)
(Wd , y)0 along CD.		(5)

uL,uR,uB

are solutions to homogeneous

(Laplace) equation, and are chosen in order for

(x, y) to satisfy the rest of the boundary condition namely, on the left, the right, and the

A natural choice for v(x, y) is approximated as:

v(x, y) S

Vg V fb S

3tox

(8)

This point corresponds to the point of maximum barrier height. It is close to the mid point of the channel when the drain voltage is low. When the drain voltage is high, the point of highest barrier moves closer to the source.

3tox x 0,

and

for the oxide region,

So the threshold voltage of device can be calculated by the following relation

2

V V

2

• tox SiGe

x

v(x, y) S

1

qNa

2 SiGe S

(9)

th fb

bi

ox

x x0, y yc

0 x Wd .

for the Channel region,

4.4

SIMULATION

variation in electron affinity due to Ge Content in SiGe

Here long channel surface potential S

is related to Vg by the requirement that be continuous at x 0:

v / x

electron affinity in strained silicon(eV)

4.35

4.3

Vg V fb

S

• 2qNa

S

4.25

3tox

si Ge

(10)

4.2

v and

v / x are zero at

x Wd

is the long-

4.15

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35

Ge content

channel depletion width given by

Figure : Electron affinity in strained silicon Vs.

Germanium content in SiGe alloy.

Wd

2 siGe S

qNa

(11)

The third series, uB , however, cannot be treated similarly, since

exp n (Wd 3tox ) / L decreases much more

n

b

slowly with n. fortunately, the coefficients d * are

at least an order of magnitude less than

* and

1

c* combined. The entire u series can therefore

1 B

be neglected altogether.

variation in Strained silicon energy band gap due to Ge Content inFSigiGuere : Comparison between energy band gaps

1.1

for strained silicon and SiGe alloy.

Energy band gap in strained silicon(eV)

1.08

1.06

1.04

1.02

1

0.98

0.96

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35

Dielectric Constant of SiGe

Ge content

13.4

13.2

13

12.8

Dielectric Constant of SiGe Vs. Ge Content in SiGe

Figure : Energy band Gap in strained Silicon Vs. Ge content

12.6

12.4

12.2

Energy band gap in Silicon-Germenium alloy(eV)

1.1

1.05

SiGe energy band gap variation due to Ge Content in SiGe

12

11.8

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35

Ge Content

1 Figure : Dielectric Constant of SiGe alloy Vs.

Ge Content

0.95

0.9

0.85

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35

Ge content

Figure : Energy Band Gap in silicon- Germanium alloy Vs. Ge Content

Comparision B/W SiGe and Strained Silicon Energy Band Gap due to Ge Content in SiGe

1.1

Energy Band Gap(eV)

1.05

1

0.95

0.9

0.85

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35

Ge Content

I-V characteristics of Strained Si/SiGe n-channel MOSFET

0.0012

0.0010

0.0008

0.0006

0.0004

0.0002

0.0000

0 0.5 1 1.5 2

2.5

Drain Voltage(V)

Vds=1V Vds=1.5V

Vds=2V

Drain Current(A)

Drain Current(A)

Figure : I-V Characteristic of a 0.25µm strained Si/SiGe n-channel MOSFET. The device width is 9.5µm.

0.0012

Id-Vg curve for 0.25µm strained Si/SiGe n- channel MOSFET

0.0010

0.0008

0.0006

0.0004

0.0002

0.0000

0.00 0.50 1.00 1.50 2.00 2.50

Gate Voltage(V)

Figure : Id-Vg curve for 0.25µm strained Si/SiGe n-channel MOSFET. The device width is 9.5µm.

CONCLUSION

Vg=1V

Vg=1.5V Vg=2V

Vg=2V(Bulk Si MOS)

The work presented here shows the performance of a 0.25µm strained Si/SiGe n- channel MOSFET. In this work, the behavior of MOSFET is observed with the help of OrCAD simulation software. The effect of Ge concentration in strained Si/SiGe channel is seen. SiGe band gap is affected more by Ge introduction in SiGe compared to that of strained silicon band gap. Strain generated in channel increases the mobility of electrons in MOSFET that enables that device to be used for high speed operation and due to low threshold voltage it also takes less power for their operation. Hence one can say that this strained Si/SiGe n-channel MOSFET can have tremendous applications in modern communication equipment and biomedical field.

The present work can be extended to a device with different doping profile concentrations. The speed of operation can be enhanced by use of other combination of alloy in the channel. Hence one can analyze the current behavior of the device with different alloy combinations. Analytical model for obtaining current can also be done to validate the simulated results. Performance of a device with high dielectric constants may also be evaluated by using this model.

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