Reduction of Partial Products for Vedic Multiplier

Reduction of Partial Products for Vedic Multiplier

Mr. Sunil Patel

Dept. of Electronics And Communication G.H.Patel college of Engineering And technology Vallabh Vidhyanagar, India.

Prof. Deepak Parashar

Dept. of Electronics And Communication G.H.Patel college of Engineering And technology Vallabh Vidhyanagar, India.

Abstract Multiplier is one of the most important components of many high performance digital systems. And also it is one of the most power consuming and time consuming component of the digital systems. So optimization of multiplier is very important in process of making system fast and power efficient.

This paper present multiplier based on Vedic method "Urdhava Tiryakbhyam" Method which is also known as vertically and crosswise method. This multiplier used 2x2multiplier blocks as basic building block. This paper suggest multiplier of 8×8 multiplier we should use 2×2 multiplier in place of 4×4 multiplier. As we have to many partial product with using 2×2 multiplier it look very complex and timely process of adding it. But adding the numbers in method describe in this paper make it simpler. QUARTUS tool is used for simulation and time analysis.

Keywords Vedic multiplier; Reduction of partial products; vertically and crosswise; Urdhava Tiryakbhyam Multiplier; 8×8 multiplier.

General Terms Vedic multiplier= vertical and crosswise multiplier or Urdhava multiplier

CSA= carry save adder

1. INTRODUCTION

   Multiplication is one of the most used processes in digital systems and processors. Also it required plenty of adder and partial product generators. It can be said that multiplication is one of most time consuming and power consuming process. Due to this it is necessary to optimize the multiplier before finalizing any digital design.

   Vedic multiplication techniques are simple formulae which can be used for solving number of different types of mathematical problems. This paper shows design of 8×8 multiplier Urdhava Tiryakbhyam.

   In this design 16 parallel 2×2 multiplier blocks are used as partial product generator. Then partial product is reduced to 7 using reduction. This remaining seven numbers are then added accordingly to find the product of the two numbers.

2. URDHAVA TIRYAKBHYAM

   The Urdhava Tiryakbhyam is also known as vertically and crosswise. In this method partial product are simultaneous generated using partial product generators. And then they are added vertically and crosswise. This

   method can be applied on every numbers to find their multiplication.

   Fig. 1: Urdhava Tiryakbhayam

   This figure shows multiplication of two decimal number using Urdhava Tiryakbhayam method. In this multiplication we four partial products and then added to find the product.

3. VEDIC MULTIPLIER

   Fig. 2: Vedic Multiplier

   This figure shows the use of Urdhava Tiryakbhyam method in binary multiplication. Various research papers are based on this architecture. Same method is used in design of 16×16 and 32×32 multiplier using n/2 multiplier as partial product generator. Cary save adder is used to make multiplier faster as it is faster way to covert 3 number

   into 2 number than addition of two number can be carry out with any addition method.

   Now in this paper, proposed architecture is based on use of 2×2 multiplier as partial product generator.

4. PROPOSED ARCHITECTURE

   1. Generation of partial products

      Fig. 3: Partial profuct genration using 2×2 multiplier blocks

      Here a(7,0)and b(7,0) are two 8 bit numbers that need to be multiply. 2×2 multiplier are used to generate 16 partial products. Every partial product is generate from multiplication of consecutive bits from both numbers.

      Like,

      p1=a(7,6) x b(7,6)

      p2=a(7,6) x b(5,4)

      Other partial products are generate in same manner as shown in figure. Different partial product has different multiplying factor.

      Now during addtion every partial product has different value. For example p1 multiplying factor of 212 due to its inputs a7a6 is actually a7a6 x 26 and b7b6 is actually b7b6 x26. Like this multiplying factors of all partial products are varying from 212 to 20. 20 is multiplying factor for p16 during addition because it is multiplication of both LSB.

   2. Reduction of partial products

   Due to difference significance or different multiplying factors of partial products, some numbers doesnt even need to be added but just put them together according to their significance like following example,

   Here, first number has significant digit start after 4th digit and second number has not any significant number after 4th digit. In this case their addition is simply to write them together.

   Multiplying factor of partial products are varying from 212 to 20. All partial products have only four significant digits as they are outputs of 2x2multiplier. This method can be used on following combinations.

   212(a1)	28(a3)	24(a8)	20(a16)	X1(16-bit number)
   	210(a2)	26(a4)	22(a12)	X2(12-bit number)
   	210(a5)	26(a7)	22(a15)	X3(12-bit number)
   		28(a6)	24(a11)	X4(8-bit number)
   		28(a9)	24(a14)	X5(8-bit number)
   			26(a10)	X6(4-bit number)
   			26(a13)	X7(4-bit number)

   After applying this reduction 16 partial products are reduce into 7 numbers. These numbers can be added like following.

   q1=x2+x3 q2=x4+x5 q3=x6+x7

   Product= q1+q2+q3

5. SIMULATION AND RESULTS

   The 8×8 multiplier with the use of 2×2 blocks is designed in VHDL and function verification is done. Multiplier is simulatated with various inputs and results are checked.

   Fig 4 : fucntional simulation of proposed multiplier

   a[7..0]

   b[7..0]

   twobitmultiplier:x1

   A0 C0

   A1 C1

   B0 C2

   B1 C3

   twobitmultiplier:x3

   A0 C0

   A1 C1

   B0 C2

   B1 C3

   twobitmultiplier:x8

   A0 C0

   A1 C1

   B0 C2

   B1 C3

   Add3

   A[13..0]

   1' h0 –B[13..0] +

   ADDER

   3' h0 —

   A[11..0]

   B[11..0]

   Add5

   +

   ADDER

   c[15..0]

6. CONCLUSION AND FUTURE WORK

   In this paper we used 2x2multiplier as partial product generator. Due their significance difference in partial products in this method, partial products are easily reduced using above mentioned technique. Reduction of partial product 16 to 7 greatly reduce the adding effort that normally as now only 7 number need to be added. Of

   twobitmultiplier:x16

   A0 C0

   A1 C1

   B0 C2

   B1 C3

   twobitmultiplier:x2

   A0 C0

   A1 C1

   B0 C2

   B1 C3

   twobitmultiplier:x4

   A0 C0

   A1 C1

   B0 C2

   B1 C3

   twobitmultiplier:x12

   A0 C0

   A1 C1

   B0 C2

   B1 C3

   twobitmultiplier:x5

   A0 C0

   A1 C1

   B0 C2

   B1 C3

   twobitmultiplier:x7

   A0 C0

   A1 C1

   B0 C2

   B1 C3

   1' h0 —

   Add0

   A[12..0]

   1' h0 –B[12..0] +

   ADDER

   course numbers have different digits but still it is helpful in reduction of component and ime delay effectively. Due to this, proposed architecture is improvement over overly used Vedic Multiplier Architecture.

   This method can be used for higher bit multiplications and addition also can be optimized. Even after reduction of partial products still 7 numbers with different multiplying factor and different digits is available. Different optimizing method can be used to simplify the addition.

7. REFERENCES

1. Jagadguru Swami, Sri Bharati Krisna, Tirthaji Maharaja, Vedic Mathematics or Sixteen Simple

   twobitmultiplier:x15

   Mathematical Formulae from the Veda, Delhi (1965),

   A0 C0

   A1 C1

   B0 C2

   B1 C3

   twobitmultiplier:x6

   A0 C0

   A1 C1

   B0 C2

   B1 C3

   twobitmultiplier:x11

   1' h0 —

   Add1

   A[8..0]

   1' h0 –B[8..0] +

   2' h0 —

   Add4

   A[6..0]

   B[6..0] +

   Motilal Banarsidas, Varanasi, India, 1986.

2. M.E Paramasivam, and R.S Sabeenian, An efficient bit reduction binary multiplication algorithm using Vedic methods, IEEE 2nd International Advance Computing conference, Patiala, India, pp. 25, 19-20 Feb. 2010.

   A0 C0

   A1 C1

   B0 C2

   B1 C3

   ADDER

   ADDER

3. L. Sriraman, and T. N. Prabakar, Design and Implementation of Two Variable Multiplier Using KCM

   twobitmultiplier:x9

   A0 C0

   A1 C1

   B0 C2

   B1 C3

   twobitmultiplier:x14

   and Vedic Mathematics, IEEE, 2012.

4. Parth Mehta, Dhanashri Gawali,Conventional versus Vedic mathematical method for Hardware implementation

   A0 C0

   A1 C1

   B0 C2

   B1 C3

   twobitmultiplier:x10

   A0 C0

   A1 C1

   B0 C2

   B1 C3

   1' h0 —

   Add2

   A[4..0]

   1' h0 –B[4..0] +

   ADDER

   of a multiplier,IEEE,2009

5. Himanshu Thapliyal and M.B. Srinivas, High Speed efficient N X N Bit Parallel Hierarchical Overlay Multiplier Architecture Based On Ancient Indian Vedic Mathematics, transactions on engineering, computing and

   twobitmultiplier:x13

   A0 C0

   A1 C1

   B0 C2

   B1 C3

   Fig 4. RTL view of propsed architecture

   8×8 multiplier comparisons

   technology v2 december 2004 issn 1305-5313

6. Sumit Vaidya and Deepak Dandekar. Delay-Power Performance Comparison Of Multipliers In Vlsi Circuit Design, International Journal of Computer Networks & Communications (IJCNC), Vol.2, No.4, July 2010

ABOUT AUTHORS:

Mr. Sunil Patel:

He is the PG scholar at G.H.Patel college of engineering and Technology. He is pursuing his master in field of Embedded system. He has completed is bachelor degree in the field of electronics and communication engineering from the Sardar vallabhbhai National Institute of Technology (SVNIT), Surat, India. His area of interest is digital design on FPGA.

Prof. Deepak Parashar:

Currently he is working as assistant professor at G.H.Patel college of Engineering and Technology. He area of interest is VLSI design.