Simulation And Control Of Transformer Less Unified Power Quality Conditioner For Power Quality Improvement

Simulation And Control Of Transformer Less Unified Power Quality Conditioner For Power Quality Improvement

Simulation And Control Of Transformer Less Unified Power Quality Conditioner For Power Quality Improvement

Sruthi Raghunath

PG Scholar, Department of EEE Karunya University, Coimbatore, India

1. Venkatesh Kumar Assistant Professor, Department of EEE Karunya University, Coimbatore, India

   Abstract The major issue in the power distribution system is the power quality. The increase in the proportion of sensitive equipments in production processes also increases the demand of the power quality improvement. With the extensive improvement in power electronics field, the implementation of power electronics to improve power quality provides effective solutions to power quality problems. One of the most effective solutions to power quality issues in the distribution side is the installation of Unified Power Quality Conditioner (UPQC). UPQC is supported for alleviating all the voltage and current related problems. In this paper, the conventional injection transformer is replaced with capacitor which injects voltage to the line. With the use of capacitor, the drawbacks of the injection transformer are reduced and thus are more efficient. The cross phase connected UPQC enables to overcome the problems related to single line faults also. The cross phase connection enables injection to a faulty phase from a healthy phase. The control strategy implemented is much similar to DVRs. This scheme was found beneficial and the simulation (using MATLAB/SIMULINK) results prove that the voltage and current control was found good and the harmonics in the system were also reduced.

   Keywords: Power Quality; UPQC; Harmonics; Voltage Source Converters (VSC)

   1. INTRODUCTION

      Power quality phenomena include all situations in which the supply voltage (voltage quality) or load current (current quality) waveforms deviate from the sinusoidal waveform at rated frequency with amplitude corresponding to peak value for all the phases for any three-phase system.

      In recent years, the term Power Quality (PQ) has gained significant importance, especially in electrical distribution side. As per international standards, the term power quality can be defined as the physical characteristics of the electrical supply provided under normal operating conditions that do not disrupt or disturb the user's processes.

      The disturbances in voltage (harmonics, sags, swells) may cause the tripping of sensitive electronic equipment which can lead to disastrous consequences in industrial plants, such as, unexpected results or a termination of the whole production line. These events are common in industrial sectors and cause high economical damage. In the above scenario, it is the source that disturbs the load/ sensitive equipment. To avoid heavy economical losses, the industrial customers often install

      mitigation devices/ equipments to protect their own plants from such kind of disturbances.

      The growing use of power electronics based equipments in modern plants is resulting in a load which is sensitive and harmonics producing in nature. Interestingly, these equipments generally produce distortion in currents and/or voltages. Thus, there is a new trend to install mitigating equipments that can serve the dual purpose, to both the utility as well as to the customer. Thus with the implementation of Custom Power Devices in the distribution side, Power Quality is enhanced.

      One of the most effective solutions to power quality issues in the distribution side is the installation of Unified Power Quality Conditioner (UPQC). UPQC is supported for alleviating all the voltage and current related problems (imbalances, Harmonics etc). Conventional UPQC [1] is constituted of two Voltage Source converters (VSC), an injection transformer and a common dc link. The presence of injection transformer can create problems like offset due to energisation of transformers, increased losses in transformer windings and high cost of the system. Thus there is a need for a better injecting device. A DC isolation circuit was proposed in [4]. This implementation increases the complexity of the system along with the increase in the cost of the system. Thus, here in this paper, injection transformer as well as the DC isolation circuit is replaced with a series capacitor which acts as Voltage Injecting source to the line. With the use of a series capacitor as injecting device [5], the cost and the complexity of the system is reduced and the system was found more efficient.

      The conventional UPQC can eliminate three phase faults alone. The system remains idle for single phase faults. The cross phase connected UPQC enables to overcome the problems related to single line faults [6]. The cross phase connection enables injection of voltage to a faulty phase from a healthy phase. The cross connection in phase is given at the load side as shown in Fig. 1. Unlike conventional UPQC, here each phase is implemented with half bridge configuration VSCs and separate DC links for each phase. This configuration provides better control of each phase keeping the cost also minimal.

      Control scheme of the proposed UPQC is also considered here in this paper. Various control strategies have been proposed for UPQC. Some of them are PQ theory [7], wavelet

      transform [9], neural networks [10], fuzzy algorithm [11], Fourier transform theory [8], State feedback control law [2], power angle control (PAC) concept [13].

      Fig 1 Single line diagram for the proposed system with cross connected

      phase at load side

      In this paper, the control strategy implemented is much similar to DVRs. The control strategy of a transformer-less DVR is discussed in [5]. The control is implemented based upon the series capacitor voltage and the inductor current feedbacks. The design of the series capacitor and the inductors are obtained from [15].

   2. SYSTEM DESIGN

      1. Basic System Design

         The basic circuit diagram of the proposed system is shown in Fig. 2. The series and shunt VSC is not the conventional full bridge configuration. There are three UPQC modules corresponding to each phase. Each module consists of two VSCs in half bridges configuration and a split capacitor DC link. Out of the two half bridges, one acts as the series VSC

         Fig 2 circuit diagram for the proposed strategy

         The control signals for the series is provided as depicted in Fig 3.The design for the system is based on the control system analysis. From the flowchart, we obtain control block diagram as shown in Fig. 4. The various parameters of the system are obtained by obtaining the overall closed loop transfer function and then performing stability analysis on the system. Based on the stability analysis results and selecting a desired damping ratio, the parameters are calculated.

         Reference Voltage Generated

         and other as Parallel VSC. The system is more efficient because of different DC link voltages corresponding to different phases. Whenever a fault occurs, the system restores immediately and more efficiently. The UPQC module for phase A is shown in Fig 3. Unlike the conventional UPQC, here the

         Actual capacitor Voltage

         Error Voltage

         Compare the 2 voltages

         ability to eliminate faults occurring due to the single phasing is obtained. Cross phase connection enables the system to eliminate this fault. The elimination of single phase fault can be

         PD Controller

         Virtual Inductor Current

         explained very well. The shunt VSC of the Phase C is

         connected to Phase A o the load terminal, when Phase C has a single phase fault occurred. The current in Phase A is absorbed by the shunt VSC and the series VSC for phase C works. This enables injecting series voltage via the capacitor. The magnitude and phase of the injected voltage in this case will be same as Phase C since the module corresponding to phase C works here. This advantage of the proposed system can widely used.

         Current through filter L1

         +

         – +

         – +

         Current through

         capacitor C1

         Current Error

         Current Error Gain

         DC link Voltage

         PWM

         Controller

      2. Controller For Series VSC

         The main aim of the series VSC is to compensate for voltage imbalances. For any system, when there are imbalances, the voltage can be resolved into three components. The positive sequence will be always in phase with the supply system.

         Series VSC Switches

         Series VSC Switches

         Fig 3 – Flowchart for the Series VSC controller

         Fig 4 – Control Block diagram Series VSC

         Here PWM controller is modeled as a unity gain system (KPWM = 1). From the total transfer function of the system, Vca1, which is the actual capacitor voltage, is obtained as in the equation below:

         1 = 1V1 + 2 (1)

         ca1

         ca1

         Where, G1 and G2 are transfer function with input V* (Capacitor Voltage calculated) and isa (Source current) respectively. Thus transfer function G1 and G2 will consist of all the parameters K1 (Current Error gain), Kp (Proportional Gain of PD controller) and Kd (Derivative gain of PD

         qs = 0

         I*

         LPF

         Cpq -1

         I*

         Power of source

         Power of source

         Power losses in UPQC

         Power losses in UPQC

         Total power

         Cos(wt + p )

         Vsd

         sin(wt + p )

         SPLL

         Supply voltages

         controller)

         From calculation, the values were found to be K1 = 25, Kp

         =26 & Kd = 0.005. Thus the control system for series VSC was analysed and the switching frequency of the IGBT switches of series UPQC used was 5 KHz.

      3. Controller For Parallel VSC

      The major concern for the parallel VSC is to compensate

      to abc transformation

      Ia* Ib* ic*

      Fig 4 Reference current generation

      Reference Current Generated

      for unbalances and reactive power components of the load currents and reduce the harmonics in the current. Here a reference current is generated based on the power balance theory and instantaneous power theory. By applying power balance relationship & the theory of instantaneous active power and reactive power we obtain the reference current in –

      DC reference current

      Actual line current

      Current error

      Compare the 2 Currents

      reference frame. Here P

      LOSS

      is calculated as the power loss in

      gain

      the resistors through which UPQC module is connected to the lines.The reference current generation in abc reference frame is depicted in Fig 4

      Thus the reference current generated in – reference frame

      +

      +

      Virtual Inductor Current

      Current error gain

      Current error gain

      Sum of load

      is transformed using C

      -1 matrix which is as given below:

      Current through

      – + – currents of this

      i

      pq

      1

      filter L2

      phase & next phase

      = 1

      =

      (2)

      i

      Voltage Error

      Where, the voltages V , V are given as below

      V = Vsd cos (wt + p )

      V = Vsd sin( wt + p )

      Difference in line voltages of next phase &

      Gain

      parallel VSC Switches

      parallel VSC Switches

      –

      +

      +

      PWM

      Controller

      Vsd

      is the positive sequence component of supply. The

      this phase

      reference current generated in – reference frame is converted

      Fig 5 Flow chart for parallel VSC

      b

      b

      sc

      sc

      to abc reference frame. And we obtain current Isa*, Is *and I *

      for phases A, B and C phases respectively.

      DC Reference voltage for entire link

      + PI Controller

      –

      Phase angle of the phase to which shunt VSC is connected

      X

      Actual DC voltage in capacitor 1

      +

      +

      + Voltage error gain

      –

      +

      + Idc* – DC link reference current

      Actual DC voltage in capacitor 1

      Fig 6 DC link reference current generation

      The flowchart for the parallel VSC control is shown in Fig

      1. The DC link reference voltage is calculated with the following formulae (Where m= modulation index & here m is chosen as 1).

         500

         400

         300

         200

         Voltage in Volts (V)

         Voltage in Volts (V)

         100

         Fault applied

         Source Voltage Without UPQC

         Harmonic Load is switched

         V 2

         2VLL

         (3) 0

         dc 3m

         -100

         -200

         DC link reference current is obtained as in Fig 6. The control block diagram of the parallel VSC is shown in Fig 7. From this control block diagram, we obtain the parameters K2 (Current error gain), K3 (Voltage error gain) by performing stability analysis on transfer function G3. Here again PWM controller is modelled as Unity gain system (KPWM = 1)

         The four transfer functions for the system is obtained as below

         -300

         -400

         -500

         Harmonics Load Applied

         Fault Applied

         Harmonics Load Applied

         Fault Applied

         150

         100

         50

         Current (A)

         Current (A)

         0

         0 0.1 0.2 0.3 0.4 0.5

         Time in seconds

         Fig 9(a) supply voltage with fault

         Source Current Without UPQC

         3

         4

         = 2 3

         2 S+ (2 +3 +2 3 )

         = 2 3

         -50

         -100

         -150

         S+ ( + + )

         -200

         2 2 3 2 3

         0 0.1 0.2 0.3 0.4 0.5

         Time in Seconds

         5

         = 1

         2 S+ (2 +3 +2 3 )

         Fig 9(b) supply current with fault

         With the implementation of the proposed UPQC, the voltage

         6

         6

         = 2 S+ 2 +3 3

         2 S+ (2 +3 +2 3 )

         Where G3, G4, G5 and G6 are the closed-loop transfer functions

         sag was found almost zero. The output waveforms are represented in Fig 10 (a) & (b). The Total Harmonics Distortion (THD) is tabulated as in table I.

         Sb

         Sb

         between the reference I and iSb

         , the DC-link voltage

         Source Voltage With UPQC

         Sag eliminated Harmonics eliminated

         Sag eliminated Harmonics eliminated

         500

         DCa

         DCa

         regulating current reference I

         and iSb, the voltage

         400

         disturbance VLb 2 VLa and iSb, and current disturbance iLb – ib2 to iSb respectively. = 1 & = (L2S + R2)/ (K3 * KPWM + 1). The values used here in this paper are K2 = 15, K3 = 10.

         300

         200

         Voltage (V)

         Voltage (V)

         100

         0

         -100

         -200

         -300

         -400

         7 Control block diagram for parallel VSC

         -500

         Fault minimized

         Harmonics Reduced

         Fault minimized

         Harmonics Reduced

         50

         0 0.1 0.2 0.3 0.4 0.5

         Time in Seconds

         Fig 10 (a) Supply voltage with UPQC

         Source Current With UPQC

         40

   3. SIMULATION RESULTS

The scheme was verified using Matlab/SIMULINK 7.10.0 version. A supply of 415 V, 50 Hz and a symmetric load of 70KW was applied to the system. A harmonics load with an RL load (5, 10mH) is also switched to the system. The outputs were obtained for three phase faults as well as single phase faults.

1. Three Phase Faults

   30

   20

   Current (A)

   Current (A)

   10

   0

   -10

   -20

   -30

   -40

   0 0. 0.2 0.3 0.4 0.5

   Time in Seconds

   Fig 10 (b) Supply current with UPQC

   The system is applied with a three phase symmetrical fault during 0.1 s to 0.2 s. At the time period from 0.3 to 0.4 s, a harmonics load is switched to the system. The voltage and current waveforms are as shown below in fig 9(a) and (b) below.

2. Single Phase Faults

A single phase fault is implemented in phase C. This fault is introduced between 0.1 s and 0.3 s. The voltage & Current is depicted in the Fig 11 (a) & 11 (b).

300

200

100

Voltage (V)

Voltage (V)

0

-100

-200

-300

400

300

Source Voltage With Single phase Fault

Single Phase Fault At phase C

Single Phase Fault At phase C

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

TIme in Seconds

Fig 11 (a) Voltage during single phase fault at Phase C

Source Current with Single Phase Fault

1000

900

800

700

DC voltage

DC voltage

600

500

400

300

200

100

0

DC link Voltage

0 0.1 0.2 0.3 0.4 0.5

Time in Seconds

Fig 13 DC link Voltage

IV. CONCLUSION

Single Phase Fault applied

Single Phase Fault applied

200

100

Current (A)

Current (A)

0

-100

-200

-300

-400

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.

Time in Seconds

Fig 11 (b) Current during single phase fault Phase C

The cross phase connection of the UPQC enables the elimination of this fault by supplying from phase A which is healthy. The supply voltage and current waveform after compensating using a cross-phase connected UPQC is shown in Fig 12 (a) & (b) respectively.

Source voltage with UPQC – Single Phase fault

500

400

300

200

Voltage (V)

Voltage (V)

100

0

-100

-200

-300

-400

-500

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

TIme in Seconds

Fig 12(a) Supply voltage after compensation using UPQC

The paper deals with the major power quality problems like voltage sag, current harmonics which were minimized with the implementation of the cross phase connected UPQC. The topology of a cross-phase-connected UPQC is introduced and two multi-loop control schemes are incorporated for the series and parallel VSC within the proposed UPQC. Extensive simulations using Matlab/SIMULINK are carried out to verify the practicability of the configuration and the effectiveness of the proposed control schemes under various operating conditions. The use of cross phase connected UPQC has been found effective in compensating for three phase faults and single phase faults. The use of continuous feedback from the capacitor voltage for the series VSC and the inductor & line currents for the parallel VSC enabled a better reference generation thus, a better output.

40

30

20

10

Current (A)

Current (A)

0

-10

-20

-30

-40

Source Current With UPQC – Single Phase Fault

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

Time in Seconds

Fig 12(a) Supply current after compensation using UPQC

Table I Comparison of Total harmonics Distortion (THD)

The voltage sag due to three phase symmetrical fault was found to be 67.21% and it was found to be 100% compensated using a cross phase connected UPQC. The single phase fault induced in any phase was also effectively eliminated with the use of cross phase connected UPQC. The voltage sag during the period of single phase fault in phase C was found to be 92%. But with the implementation of UPQC, the sag was

The DC link voltage was designed to work for 1050 V. Here in the simulation, we obtained a DC link voltage of about 970

V. The DC link voltage waveform obtained is shown in Fig 13.

almost eliminated to 100%.

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