Simulation of a Novel Phase-Shift Operated Interleaved Snubberless Current-Fed Half-Bridge Dc/Dc Converter

Simulation of a Novel Phase-Shift Operated Interleaved Snubberless Current-Fed Half-Bridge Dc/Dc Converter

Savyasachi. G. K

Dept. of Electrical and Electronics Engineering,

The National Institute of Engineering,

Mysore, Karnataka, India.

Radha. R

Dept. of Electrical and Electronics Engineering,

The National Institute of Engineering,

Mysore, Karnataka, India.

Dr. A. D. Kulkarni

Dept. of Electrical and Electronics Engineering,

The National Institute of Engineering,

Mysore, Karnataka, India.

Abstract – This paper proposes a phase-shift operated interleaved snubberless current-fed half-bridge dc/dc converter with single-phase unfolding inverter. It is suitable for grid- tied/utility interface as well as off-grid/standalone application based on the mode of control. Two snubberless current-fed half- bridge isolated dc/dc converters are interleaved in parallel input and series output configuration. The proposed converter attains clamping of the device voltage by secondary modulation, thus eliminating the need of snubber or active-clamp. Phase-shift operation is proposed to control these two converter cells, which generate a rectified sinusoidal pattern at the dc link. A simple H-bridge unfolding inverter with line frequency switching square-wave control is used to produce single-phase sine voltage. This not only simplifies the inversion stage in terms of modulation but also reduces the switching losses. Steady-state operation, analysis and design procedure are presented. Simulation results using PSIM 9.3 are obtained to verify the

photovoltaic generation is a flexible power generation technique which is scalable from small-scale residential application to large-scale solar farms/power plants.

FUEL CELL

PV Panel

PMSG

DC TO AC

DC TO AC

POWER CONVERTER

AC Utility Grid

proposed analysis and design.

Keywords – Current-fed half-bridge (CFHB) converter, High frequency transformer (HFT), Interleaved, Phase-shift operation, Snubberless.

FOSSIL FUEL GENERATORS

ENERGY STORAGE

LOAD

1. INTRODUCTION

   In last few decades, the difference between global energy demand and limited availability of fossil fuels due to fast depletion has exponentially increasing which has resulted in change of focus towards renewable energy sources. In order to cover this increasing global energy demand and supply gap, solar energy is proving to be one of the most promising solutions.

   Alternate/distributed energy sources like solar, wind, etc. produces unregulated and discontinuous output and, therefore cannot be used in its original form. A power conditioner is essential to obtain a regulated and stable output in useful form across the load. This also assists in extracting the maximum power from the source. These energy sources are integrated together with the energy storage for back-up power to form a distributed generating system focusing on long-term sustainability.

   The distributed generation system is close to electricity users. Such a typical system is shown in Fig.1. Solar

   Fig.1: Hybrid distributed power generation system.

   Photovoltaic power supplied to the utility grid is gaining more and more visibility, while the worlds power demand is increasing. Not many PV systems have so far been placed into the grid due to the relatively high cost, compared with more traditional energy sources such as oil, gas, coal, nuclear, hydro, and wind. The price of the PV modules were in the past the major contribution to the cost of these systems. The price for the PV modules has dropped significantly over past few years due to mass production and expected to be cheaper in future. Solid-state inverters have been shown to be the enabling technology for putting PV systems into the grid.

   The cost of the grid-connected inverter is, therefore, becoming more visible in the total system price. A cost reduction per inverter watt is, therefore, important to make PV-generated power more attractive. Focus has, therefore, been placed on new, cheap, and innovative inverter solutions, which has resulted in a high diversity within the inverters, and new system configurations.

   Various circuit topologies for small distributed power generators are presented, compared, and evaluated against the requirements of power decoupling and dual-grounding, the capabilities for grid-connected or/and stand-alone operations is presented in [1]. In [2], various inverter topologies for connecting PV modules to a single-phase grid are presented, compared, and evaluated against demands, lifetime, component ratings, and cost.

   A new class of converters based on the inductive input converters for the design of a power electronic interface for fuel cell applications is proposed in [3]. Flexible choice of components, low losses, high efficiency, and modular

   modulated and two converter cells are operated with sinusoidal phase-shift between them at line frequency. Fig.2 shows the block diagram of the proposed topology.

   The objectives of this paper are as follows: steady-state operation and analysis with secondary modulation technique and phase-shift operation for the proposed topology are discussed in Section II. A complete design procedure has been illustrated by a design example in Section III. Simulation results using PSIM 9.3 are given in Section IV to verify the proposed analysis and design.

   DC

   Supply (PV

   Panel)

   L O A D

   Phase-Shift Operated

   converter possibility are all interesting characteristics of these converters. [4] presents the implementation of an interleaved boost converter (IBC) using SiC diodes for PV applications. The converter consists of two switching cells sharing the PV panel output current. Their switching patterns are synchronized with 180 phase shift. In [5], a single-phase grid-connected transformerless photovoltaic inverter for residential application is presented. The inverter is derived

   Interleaved Snubberless Current-Fed Half-Bridge Dc/Dc Converter

   Unfolding Inverter

   Gate Drive Circuit

   from a boost cascaded with a buck converter along with a line frequency unfolding circuit.

   In [6], a PV module integrated converter is implemented with a current fed two-inductor boost converter cascaded with a line frequency unfolder. The current source is a sinusoidally modulated two-phase buck converter with an interphase transformer. Different topologies of appropriate inverter systems in the medium power range of 20 kW and higher are presented briefly in [7]. The study includes transformerless inverters as well as two-stage inverter systems with high- frequency transformers.

   A new active clamping CFHB converter is presented in

   [8] & [9]. [10] proposes a wide range ZVS active-clamped L- L type current-fed isolated dcdc converter. In [11], a new ZCS-PWM current-fed dcdc boost full-bridge converter is introduced and a comparison is made between two converter topologies – the standard ZVS active-clamp topology and a new ZCS topology.

   A novel snubberless CFHB front-end isolated dc/dc converter-based inverter for PV applications is introduced in [12]. This converter attains clamping of the device voltage by secondary modulation, thus eliminating the need of snubber or active-clamp.

   A novel direct current-fed interleaved phase-modulated single-phase unfolding inverter for fuel-cell appications is proposed in [13]. Two active-clamped ZVS CFHB isolated converters are interleaved in parallel input and series output configuration. Phase modulation is used to control these two converter cells, which generate a rectified sinusoidal pattern at the dc link. A simple H-bridge unfolding inverter with line frequency square-wave control is used to produce single- phase sine voltage.

   In this paper, simulation of a phase-shift operated interleaved snubberless current-fed half-bridge dc/dc converter with unfolding inverter is presented. It consists of two converter cells connected in parallel input and series output configuration. Each converter cell is secondary

   Fig.2: Block diagram of the proposed topology.

2. STEADY STATE OPERATION AND ANALYSIS The proposed phase-shift operated interleaved

   snubberless CFHB dc/dc converter with unfolding inverter is shown in Fig.3. Two identical half-bridge current-fed dc/dc converter cells are connected in parallel to the input dc source. These two converters are modulated with a phase shift such that the phase difference between these two converters is a sine function at line frequency. Secondaries of the HFTs are connected in series followed by a full bridge rectifier. A low-pass filter is used to filter HF components of voltage to achieve rectified sinusoidal voltage across filter capacitor CO at twice the line frequency. Single-phase ac voltage is obtained by simply unfolding the rectified sine wave using the H-bridge inverter with square wave control, switching at line frequency.

   For PV application, maximum power point (MPP) tracking is performed by the front-end dc/dc converter either by varying the duty ratio or phase difference between the gate signals of two cells. Duty ratio is adjusted if the input voltage varies, and the output power is controlled by varying phase differences between the gate signals of two cells. In grid-tied mode, current injected into the grid is proportional to power available from the PV array. Control at the front end is implemented to optimize this injected current at MPP. Any traditional technique can be employed similar to the voltage- fed inverter.

   The following assumptions are made for understanding the steady-state operation and analysis of the converter;

   1. Inductors L1 L4 are large enough to maintain constant current through them over a HF switching cycle.

   2. Magnetizing inductance of the transformer is infinitely large;

   3. All the components and devices are ideal.

   4. Series inductors LS1 and LS2 represent the leakage inductance of the corresponding transformers, which are

      neglected during the analysis.

   5. Components of both the converter cells are identical.

      Fig.3: Proposed phase-shift operated interleaved snubberless current-fed dc/dc converter with single-phase unfolding inverter.

      1. Secondary modulation

         Since two converter cells are identical, for analysis purpose a single converter is considered as shown in Fig.4. In this section, steady-state operation and analysis with the ZCS concept will be explained.

         Fig.4: Current-fed half-bridge isolated dc/dc converter with full bridge on secondary.

         The front-end current-fed half-bridge converter is controlled using fixed-frequency duty cycle modulation. Before the gating signal of the primary-side switch is removed to turn it OFF, two diagonal switches on the

         respectively. Here, d is always greater than 50%, while dr is always less than 50%. Switches M3 and M6 are operated with a duty ratio of dr and switched off in synchronous with the switch M2. Similarly, the turn-off of M4 and M5 is synchronized with the turn-off of switch M1.

         Steady-state operating waveforms of the converter (Fig.4) and the circuit conditions during different intervals in a half HF cycle are explained in detail using the equivalent circuits in [14].

         Another converter is connected in input-parallel and output series configuration. Since two converter cells in proposed phase-shift operated interleaved snubberless CFHB dc/dc converter are identical (Fig.3), their operation using secondary modulation technique will be same. Switches are modulated in similar fashion with the same value of duty ratio d and dr as the first converter, except the sinusoidal phase shift between the two converter cells.

      2. Phase-shift operation

      Now the phase-shift operation of the two converter cells in the proposed converter (Fig.3) will be explained.

      secondary side are turned ON. The reflected dc link voltage

      Vdc/n appears across the transformer primary. It diverts the current from the switch into the transformer, causing

      Gate signals of switches M1

      time , which is given by

      and M3

      are phase shifted by

      transformer current to increase and the primary switch current to decrease to zero. Once current decreases below zero, the body diode across the primary switch starts conducting and the gating signal is removed causing its ZCS turn-off or natural commutation.

      The primary-side switches (M1 and M2) are operated with gating signals which are phase shifted by 1800 with an overlap. The overlap varies with duty cycle that depends on the input voltage and load conditions. The duty cycles of the primary and secondary switches are denoted by d and dr ,

      = TS /2 + · sin(t) (1)

      where TS is the time period of the HF cycle of the converter.

      represents the frequency of the desired output sine wave in radian per second.

      Magnitude of the output voltage is a function of .

      Similarly, switch pairs M2 & M4 have the same duty ratio and phase shifted by time .

      When switch M1 is turned off (t2 < t < t3 in Fig.5), voltage across the primary of the transformer, i.e., VAB, is given by

      VAB = Vin /(1-d) (2)

      Similarly, when switch M2 is turned off (t6 < t < t7 in Fig.5), voltage across the primary of the transformer, i.e., VAB, is given by

      VAB = -Vin /(1-d) (3)

      From the voltage across the transformer primary for the second converter, i.e., VCD, can be derived likewise. From the primary voltage, the voltage across the secondary of the transformer is calculated as a multiple of turns ratio n, which is the same for both the converter cells. The secondary of the transformers is connected in series and is rectified using a full-bridge diode rectifier. Vrec shows the voltage waveform at the rectifier output.

      Voltages across the primary and secondary of the transformer, i.e., VAB, VCD, and Va + Vb, are shown in Fig.5.

      Fig.5: Waveforms showing gating signals for M1M4 and voltages VAB, VCD, Va+Vb, and Vrec.[D=d].

      The rectifier is followed by a low-pass filter, which absorbs HF switching components, correspondingly resulting in average voltage Vdc across capacitor Cdc.

      For = (1d)TS, an illustration has been carried out at different instances of angle t in [13].

      From several cases discussed in [13] for different time delays, it can be observed that the voltage at the output of the filter linearly varies between the time delay of TS/2(1d)TS and TS/2+(1d)TS. Fig.6 shows the phase difference between Va and Vb varying as a function of sine over a line frequency cycle. Effective voltage at the rectifier output is also shown. PWM unipolar voltage is obtained by phase-shift operation of two converter cells.

      Voltage waveform Vdc is obtained as a function of given by

      (4)

      Rectified sinusoidal voltage is achieved at the filter output for a time delay given by Eq.1 as explained. Single-phase sinusoidal voltage is obtained by switching S1 to S4 using line frequency square-wave control. During one cycle of the rectified voltage, switches S1 and S4 are turned ON. S2 and S3 are turned ON for the following cycle, as shown in Fig.7.

      Fig.6: Waveforms of the converter for complete one cycle[13].

      Fig.7: Waveforms showing operation of the unfolding inverter circuit[13].

      Two parameters can be djusted to regulate the output voltage and power, i.e., duty ratio d of the front-end converters and maximum delay between the gating signals of two front-end converter cells. Duty ratio d can be varied within 0.50.8 if input voltage Vin varies. Output power can be controlled by varying for a given value of d at the same value Vin. At variation in input voltage Vin, the voltage across the primary devices gets affected. The voltage across the switch is given by Vin/(1d). Therefore, with an increase in Vin, d is reduced to keep the voltage across the devices below maximum value. However, variation in d does not affect the maximum output voltage of the inverter, which remains independent of d given by 4nVin.

3. DESIGN OF THE PROPOSED TOPOLOGY

   In this section, the design procedure is illustrated by a design example for the following converter system specifications:

   • input voltage Vin = 25V,

   • peak output power Po = 50 W,

   • voltage at dc link Vdc = 230 V,

   • output RMS voltage Vo = 162.63 V at fo = 50 Hz,

   • switching frequency of dc/dc converter fs = 40 kHz,

   • Switching frequency of unfolding inverter, fSi = 50 Hz.

   The duty ratio d, of dc/dc converters has to be maintained always above 0.5 to provide a current path to pass or circulate the input boost inductor currents, i.e., both the primary switches cannot be turned off at a time.

   Duty ratio d is selected as 0.75, so that output voltage can be regulated even during variation in input voltage. Here, the secondary duty ratio dr is set to 0.05.

   1. Average input current: Average input current is Iin = Po/(Vin). Assuming ideal efficiency of 100%, Iin = 2 A. Input current in each converter is half of this current since they are sharing equal current.

   2. Boost inductors: The value of the boost inductors are given by

      L1 = L2 = L3 = L4 = ( Vin . d )/( Iin . fS ) (5)

      where Iin is the boost inductor ripple current.

      For Iin = 0.2 A, L1 = L2 = L3 = L4 = 2.344 mH. Each

      boost inductor has average current rating of Iin/4 (= 0.5 A).

      The maximum voltage across the inductors is equal to

      Vdc/2n Vin.

   3. Maximum voltage across the primary switches is

      Vsw,pri = VLs + (Vdc /2n) (6) The cost of the device increases with the voltage rating.

   4. Peak current through the primary switch is Iin/2 and rated for voltage of Vdc/2n .

   5. Input and output voltages of the converter are related as Vdc = ( 2 . n . Vin )/(1-d) (7)

      For d = 0.75, the proposed converter can boost up to four times.

   6. High-frequency transformer design: Based on the primary and secondary winding currents, gauge of windings is chosen, and winding resistances are calculated.

      For the given design specifications, turns ratio of HFT from Eq.7, is n= 1.15.

      Peak value of the transformer primary current is

      ILs,peak = ( Vdc . dr )/( 2 . n . fS . LS ) (8)

   7. Leakage inductance of the transformer or series inductance

   LS is calculated using

   LS1 = LS2 = ( 2 . Vdc . dr )/( n . Iin . fS ) (9)

   The maximum voltage across the secondary switches is equal to half of the dc link voltage Vdc.

   1. DC link capacitor: Value of dc link capacitor Cdc is

      Cdc = Iin . (d-0.5) / (4 . n . Vdc . fS ) (11) Where, Vdc = allowable ripple in dc link voltage, and Cdc

      = 5.435 F for Vdc = 0.5 V. Its voltage rating is equal to Vdc

      = 230 V. Choose, Cdc = 5.435 F / 20 = 0.271 F.

   2. LC Filter: Filter inductor is calculated, assuming voltage drop across it is less than 2% of the nominal voltage. Thus,

      Lf = (Vo,rms. 0.02)/(2. f0. I0) (12)

      where f0 and I0 are the output frequency and output current, respectively. The value Lf is obtained as 23.81mH (choose 22mH or 24mH). The filter capacitor is decided according to the cut-off frequency of the low-pass filter. For this application, one-tenth of converter switching frequency fS is selected as the cut-off frequency. Capacitor is calculated as

      Cf = 1/(42 . fc2 . Lf ) (13)

      where fC is the cut-off frequency of the filter. For fC = 4 kHz, capacitor Cf is obtained as 66.48 nF (choose 68nF).

   3. Unfolding circuit: Voltage rating of the switches is selected based on the maximum voltage across Cdc, which is equal to peak value of maximum output voltage. RMS current rating of the switches are calculated as

   Isw,inv,rms = I0 /2 = Iin / (4n2) (14)

   Switches have to be rated for dc-link voltage (230V) and the current rating is 0.62A.

4. SIMULATION RESULTS

   Fig.8 shows a PSIM model of proposed interleaved current-fed phase-modulated single-phase unfolding inverter.

   Fig.9 shows the gating signals for primary switches, secondary switches.

   Fig.10-15 shows the currents through various components of the circuit.

   Fig.16-18 shows the voltage across various components of the circuit.

   Fig.19&20 shows the result of FFT analysis of the voltage across the load and the current through the load.

   From simulation results/waveforms, the efficiency and harmonics of the proposed converter is tabulated as follows;

   Circuit	Input power (Watts)	Output power (Watts)	Losses (Watts)	%
   Interleaved DC/DC converter	47.8035	45.9274	1.8761	96.075
   Unfolding inverter	44.4553	44.45	0.0053	99.988
   Proposed topology (overall)	47.8035	44.4378	3.3657	92.959

   TABLE I. EFFICIENCY

   For the given specifications, LS1

   = LS2

   = 250µF.

   The calculated value of I

   Ls,peak

   = 0.5 A.

   8. Secondary switches: The peak current through the secondary switches is

   Isw,sec,peak = Iin / (4n) (10) The calculated value is IS3,peak = 0.435 A.

   Note: = Efficiency = Output power/Input power Losses = Input power – Output power

   TABLE II. HARMONICS

   Parameter	Fundamental (50Hz)	THD (%)
   Output Voltage (Vo)	225.7 V	6.57
   Output Current (Io)	0.3761 A	6.57

   Fig.8: Proposed phase-shift operated interleaved snubberless CFHB dc/dc converter with single-phase unfolding inverter

   Vg1 Vg58

   1

   0.8

   0.6

   0.4

   0.2

   0

   1

   0.8

   0.6

   0.4

   0.2

   0

   1

   0.8

   0.6

   0.4

   0.2

   0

   1

   0.8

   0.6

   0.4

   0.2

   0

   Vg2 Vg67

   Vg3 Vg67

   Vg4 Vg58

   0 2e-005 4e-005 6e-005 8e-005 0.0001 0.00012 0.00014 0.00016 0.00018 0.0002

   Time (s)

   4

   3

   2

   1

   0

   2

   1.5

   1

   0.5

   0

   2

   1.5

   1

   0.5

   0

   Iin

   Iin1

   Iin2

   0 0.01 0.02 0.03 0.04 0.05

   Time (s)

   Fig.9: Gating signals for switches S1 to S4 (Vg1, Vg2, Vg3 & Vg4) with gate signals of secondary switches S5 to S8 (V58 & V67).

   Fig.10: Shows input current to the proposed converter (Iin) and input current to the interleaved converter cells (Iin1 & Iin2).

   Il1

   Irec

   1.2

   1

   0.8

   0.6

   0.4

   0.2

   0

   1.2

   1

   0.8

   0.6

   0.4

   0.2

   0

   1

   0.8

   0.6

   0.4

   0.2

   0

   -0.2

   1.2

   1

   0.8

   0.6

   0.4

   0.2

   0

   Il2

   Il3

   Il4

   1.5

   1

   0.5

   0

   -0.5

   -1

   1

   0.5

   0

   -0.5

   -1

   0.4

   0.3

   0.2

   0.1

   0

   -0.1

   Icdc

   Idc

   0 0.01 0.02 0.03 0.04 0.05

   Time (s)

   -0.2

   0 0.01 0.02 0.03 0.04 0.05

   Time (s)

   Fig.14: Current output from secondary full bridge (Irec), current through DC- link capacitor (Icdc) and current input to unfolding inverter (Idc).

   Fig.11: Current through boost inductors L1 to L4 (IL1, IL2, IL3 & IL4).

   0.4

   Iinv

   60

   40

   20

   0

   -20

   -40

   -60

   60

   40

   20

   0

   -20

   -40

   -60

   60

   40

   20

   0

   -20

   -40

   -60

   40

   20

   0

   -20

   Ic1 Isd1

   Ic2 Isd2

   Ic3 Isd3

   Ic4 Isd4

   0.2

   0

   -0.2

   -0.4

   0.04

   0.02

   0

   -0.02

   -0.04

   0.4

   0.2

   0

   -0.2

   -0.4

   Icf

   Io

   0 0.02 0.04 0.06 0.08 0.1

   Time (s)

   -40

   0 0.01 0.02

   Time (s)

   0.03 0.04 0.05

   Fig.15: Current output from inverter (Iinv), current through the filter capacitor (Icf) and output current through load (Io).

   Fig.12: Currents through switches S1 to S4 (Isd1, Isd2, Isd3 & Isd4) (blue) and currents through capacitor across the switches S1 to S4 (Ic1, Ic2, Ic3 & Ic4) (red).

   Ipri1

   1.5

   1

   0.5

   0

   -0.5

   -1

   -1.5

   -2

   200

   100

   0

   -100

   -200

   200

   100

   0

   -100

   -200

   Vpri1

   Vpri2

   Vsec1

   Ipri2

   1.5

   1

   0.5

   0

   -0.5

   -1

   -1.5

   -2

   1.5

   1

   0.5

   0

   -0.5

   -1

   -1.5

   Isec

   0 0.01 0.02 0.03 0.04 0.05

   Time (s)

   200

   0

   -200

   200

   100

   0

   -100

   -200

   200

   0

   -200

   Vsec2

   Vsec

   0 0.01 0.02 0.03 0.04 0.05

   Time (s)

   Fig.13: Currents through primary of HFTs (Ipri1 & Ipri2) and currents through the series connected secondary of HFTs (Isec).

   Fig.16: Voltage across primary and secondary of HFTs (Vpri1, Vpri2, Vsec1,

   Vsec2 & Vsec).

   Vdc

   250

   200

   150

   100

   50

   0

   -50

   300

   200

   100

   0

   -100

   -200

   -300

   300

   200

   100

   0

   -100

   Vinv

   Vo

   0.2

   0

   -0.2

   Mag (% of Fundamental)

   4

   3

   2

   FFT window: 2 of 5 cycles of selected signal

   0.05 0.055 0.06 0.065 0.07 0.075 0.08 0.085

   Time (s)

   Fundamental (50Hz) = 0.3761 , THD= 6.57%

   -200 1

   -300

   300

   200

   100

   0

   -100

   -200

   -300

   300

   200

   100

   0

   -100

   -200

   -300

   0 0.02 0.04 0.06 0.08

   Time (s)

   Fig.17: Voltage across DC-link (Vdc), unfolding inverter output voltage (Vinv) and output voltage across load (Vo).

   Vothd

   Vfund

   0

   0 1 2 3 4 5 6 7 8 9 10

   Harmonic order

   Fig.20: FFT analysis of output current Io.

   From Table I and Table II, it can be seen that the proposed topology has less losses and THD. By fine tuning the filter, THD can be further reduced. As the rating of the converter increases the efficiency increases and THD reduces.

5. SUMMARY AND CONCLUSION

THD

1

0.8

0.6

0.4

0.2

0

0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2

Time (s)

Fig.18: Voltage across load given as input to THD block (Vothd), fundamental component (50Hz) of Vothd (Vfund) and THD in Vothd.

FFT window: 2 of 5 cycles of selected signal

200

100

0

-100

-200

0.05 0.055 0.06 0.065 0.07 0.075 0.08 0.085

Time (s)

Fundamental (50Hz) = 225.7 , THD= 6.57%

Mag (% of Fundamental)

4

3

2

1

0

0 1 2 3 4 5 6 7 8 9 10

Harmonic order

Fig.19: FFT analysis of output voltage Vo.

This paper has proposed a novel current-fed interleaved converter that provides a secondary-side-modulation-based solution to the switch turn-off voltage spike problem. It attains clamping of the device voltage by secondary modulation, thus eliminating the need of snubber or active- clamp, making the proposed concept novel and snubberless. This reduces component count and peak current through the primary switches and transformers, has been reduced. Voltage of the primary-side switches is clamped at reflected output voltage. Therefore, a design with selection of reduced voltage rating devices is possible. Low voltage and current rating devices are less costly and result in compact converters. In addition, such devices have low ON-state resistance, resulting in reduced conduction losses, and enhance converter efficiency.

Detailed steady-state operation, analysis and design of the proposed current-fed half-bridge converter have been discussed. Phase modulation of two half-bridge current-fed converters has been proposed to generate rectified sinusoidal voltage at the dc link. This eases the design of the next dc/ac inversion stage to an unfolding circuit operating at the line frequency reducing the switching losses.

For the designed values and specifications, simulation has been carried out using PSIM 9.3.1. Simulation results/waveforms are analyzed and performances are tabulated.

In this paper off-grid system is considered. To make this system as grid connected, MPPT is incorporated between the

PV panel and the proposed converter. MPPT controls the duty cycle of the primary switches of the converter to maintain the input voltage constant. The phase of the grid voltage is taken as the feedback for synchronizing the gate pulses with the grid voltage.

The proposed converter can be commercialised since it is reliable and cost effective. It can be both off-grid and grid tied. Hence it is suitable for both small scale and large scale applications.

REFERENCES

1. Y. Xue, L. Chang, S. B. Kjaer, J. Bordonau, and T. Shimizu, Topologies of single-phase inverters for small distributed power generators: An overview, IEEE Trans. Power Electron., vol. 19, no. 5, pp. 13051314, Sep. 2004.

2. S. B. Kjaer, J. K. Pedersen, and F. Blaabjerg, A review of single-phase grid-connected inverters for photovoltaic modules, IEEE Trans. Ind. Appl., vol. 41, no. 5, pp. 12921306, Sep./Oct. 2005.

3. Y. Lembeye,V. D. Bang, G. Lefevre, and J. P. Ferrieux, Novel half- bridge inductive dc-dc isolated converters for fuel cell applications, IEEE Trans. Energy Convers., vol. 24, no. 1, pp. 203210, Mar. 2009.

4. C. N. M. Ho, H. Breuninger, S. Patterson, G. Escobar, L. A. Serpa, and

   1. Coccia, Practical design and implementation procedure of an interleaved boost converter using SiC diodes for PV applications, IEEE Trans. Power Electron., vol. 27, no. 6, pp. 28352845, Jun. 2012.

5. Z. Zhao, M. Xu, Q. Chen, J.-S. Lai, and Y. Cho, Derivation, analysis, and implementation of a boost-buck converter-based high-efficiency PV inverter, IEEE Trans. Power Electron., vol. 27, no. 3, pp. 1304 1313, Mar. 2012.

6. Q. Li and P.Wolfs, A current fed two-inductor boost converter with an integrated magnetic structure and passive lossless snubbers for photovoltaic module integrated converter applications, IEEE Trans. Power Electron., vol. 22, no. 1, pp. 309321, Jan. 2007.

7. M. Mohr, W. T. Franke, B. Wittig, and F. W. Fuchs, Converter systems for fuel cells in the medium power rangeA comparative study, IEEE Trans. Ind. Electron., vol. 57, no. 5, pp. 20242032, Jun. 2010.

8. S. Han, H. Yoon, G. Moon, M. Youn, Y. Kim, and K. Lee, A new active clamping zero-voltage switching PWM current-fed half bridge converter, IEEE Trans. Power Electron., vol. 20, no. 6, pp. 1271 1279, Nov. 2005.

9. S. J. Jang, C.-Y. Won, B. K. Lee, and J. Hur, Fuel cell generation system with a new active clamping current-fed half-bridge converter, IEEE Trans. Energy Convers.,vol. 22, no. 2, pp. 332340, Jun. 2007.

10. A. K. Rathore, A. K. S. Bhat, and R. Oruganti, Analysis, design and experimental results of wide range ZVS active-clamped L-L type current-fed dc/dc converter for fuel cell to utility interface, IEEE Trans. Ind. Electron., vol. 59, no. 1, pp. 473485, Jan. 2012.

11. A. Mousavi, P. Das, and G. Moschopoulos, A comparative study of a new ZCS dc-dc full-bridge boost converter with a ZVS active-clamp converter, IEEE Trans. Power Electron., vol. 27, no. 3, pp. 1347 1358, Mar. 2012.

12. Udupi R.Prasanna and Akshay K.Rathore Analysis, Design, and Experimental Results of a Novel Soft-Switching Snubberless Current- Fed Half-Bridge Front-End Converter-Based PV Inverter, IEEE Trans. Power Electronics, vol. 28, no. 7, pp. 3219-3230, Jul. 2013.

13. Udupi R. Prasanna and Akshay K. Rathore, Current-Fed Interleaved Phase-Modulated Single-Phase Unfolding Inverter: Analysis, Design, and Experimental Results, IEEE Trans. Ind. Electron., vol. 61, no. 1, pp. 310-319, Jan 2014.

14. Udupi R. Prasanna, Akshay K. Rathore, and Sudip K.Mazumder, Novel Zero-Current-Switching Current-Fed Half-Bridge Isolated DC/DC Converter for Fuel-Cell-Based Applications, IEEE Trans. Ind. Appl., vol. 49, no. 4, pp. 1658-1668, July/August 2013.

15. PSIM® Users Guide, Version 9.3, Release 2, July 2013, Copyright © 2001-2013 Powersim Inc.