Switched Capacitor Cascaded Multi- Level Inverter with Reduced Number of Power Switches

Switched Capacitor Cascaded Multi- Level Inverter with Reduced Number of Power Switches

Shivaprakash. T PG Scholar Department of EEE

Bannari Amman Institute Of Technology, Sathyamangalam, Erode, Tamil Nadu

Alex Stanley Raja. T Assistant Professor Department of EEE

Bannari Amman Institute Of Technology, Sathyamangalam, Erode, Tamil Nadu

Abstract-This Project presents a seven stage Multi-level inverter utilizing switched-capacitor technique. Proposed topology employs Symmetric or Asymmetric DC voltage sources as input and generates a multilevel staircase output. The structure includes a front-end switched-capacitor based DC-DC converter cascaded by a back-end H-bridge inverter. The front- end SC DC-DC converter feeds the DC voltage input to the H- bridge inverter which produces the corresponding bipolar levels. Inverters have the potential to be employed in AC microgrids where there are DC sources available. The inverter naturally solves the problem of capacitor voltage balancing as the capacitor is charged to a constant value twice every cycle. This topology also eliminates the need for series connection of individual voltage sources which require voltage balancing algorithms. For the future use we can extend by correlating either the horizontal extensions or vertical extensions.

Index term:- H- Bridge Inverter; Switched Capacitor; Voltage Balance

1. INTRODUCTON

   Multi-Level Inverter brought up in 19th century. Initially the this topology was introduce to manage the low level voltage and with higher amount of switches to perform with minimum steps of output. The smaller voltage steps lead to the production of higher power quality waveforms and also reduce voltage (dv/dt) stress on the load and the electromagnetic compatibility concerns . Some new approaches have been recently suggested such as the topology utilizing low-switching-frequency high-power devices. Although the topology has some modification to reduce output voltage distortion, the general disadvantage of this method is that it has significant low-order current harmonics. It is also unable to exactly manipulate the magnitude of output voltage due to an adopted pulse width modulation (PWM method). The section II deals with the comparison of conventional. the considerable output voltage level with the considerable number of switches[2].

   Inverter and multilevel topology. Detailed study of implementation of new multilevel inverter topology is performed in section III. Sections IV contain modulation techniques of conventional inverter topology and new multilevel inverter topology. Section V, Experimental result of two inverters is performed.

   In conventional inverters mainly two level inverters are used to obtain a controllable voltage. The two level inverter is a circuit which consists of sources with some amount of voltage and many switches for controlling voltage or current.

   In high power and high voltage applications the conventional two level inverters, however, have some limitations in operating at high frequency mainly due to switching losses and constraints of the power device ratings. Series and parallel combination of power switches in order to achieve the power handling voltages and currents. Due to the presence of many switches and sources power loss is very high. In the conventional two level inverters the input DC is converted into the AC supply of desired frequency and voltage with the aid of semiconductor power switches. Depending on the configuration, four or six switches are used. the modern multi-level inverters are used and got idea of how they cascaded together to get high number of output levels with reduced number of switches[3].

   The switching capacitor how the voltage can be boosted into number of output levels. In this the capacitor only boost the voltage level. By using the H- Bridge stepped output can be produced[4]. A group of switches provide the positive half cycle at the output which is called as positive group switches and the other group which supplies the negative half cycle is called negative group. The level of the output voltage is only half of the DC source. There is Novel modern optimized scheme are used hence the there is no DC components exists on inductor current. This topology is beneficial where unequal DC sources are available.[6]

   Then later new multi-level inverters are introduced with number of output levels are increased. There three modern inverters are there, they are Diode clamped Multi-Level Inverter, Capacitor Clamped Multi-Level Inverter, Cascade H-Bridge Multi- level Inverter. In diode clamped inverter we use diodes for rectifier as well as for controlling the sources and output. By using this method harmonics as well as using of switching can be reduced. This will produce ripples which is comparatively less than two level inverter thus obtaining a better output.

   In capacitor clamped inverters we use flying capacitor to control the voltage. We know that capacitor has the property of charging and discharging this property help the inverter for controlling the source as well as output. The voltage synthesis in a five-level capacitor-clamped converter has more flexibility than a diode clamped. cascade the two circuit with minimum number of components, not only the minimum number of component it explains how we can improve the voltage level in the output with high number of steps[1].

   A different converter topology is introduced here, which is based on the series connection of single phase inverters with separate dc sources. The resulting phase voltage is synthesized by the addition of the voltages generated by this cell.

2. MULTI- LEVEL INVERTER

   Multi-level Inverters are mostly used in industrial applications. In industries there are only high power applications generally accomplished. Even there are high power applications there is an need of low power application devices also to control and manage these application at the same time there is an inverter called Multi-level Inverter.

   Mostly the Multi- Level inverter are used as Inverter. Which means it converts the DC to AC voltage to our required level. Hence the input for multi-Level inverter is Battery, Solar Panel, Super Capacitor these are the some of the DC sources. There three types of Multi- Level Inverter are there they are Diode Clamped Multi- Level Inverter or Neutral Point Clamped Inverter, Capacitor Clamped Multi- Level Inverter or Flying Capacitor Multi- Level Inverter, Cascade H- Bridge Inverter.

   1. Diode clamped Multi- Level Inverter

      Diode Clamped Multi- Level Inverter or Neutral Point Clamped Inverter consist mainly of Diode and Power Switches, here there is an example of five level inverter is explained. This converter consists of 8 Power switches. Which means the first 4 switches are present in top section and seconds 4 switches are present at the bottom section. In between the DC voltage divide the top and bottom switches. 1st and 5th Switch are operate together, similarly 2nd and 6th switch, 3rd and 7th switch, 4th and 8th switch. In- Between these switches the diodes are clamped, hence its called as Diode Clamped Multi Level Inverter.

      Figure 2.1 Diode Clamped 5 level MLI

      The figure2.1 shows the diode clamped Five Level Multi- Level Inverter. The number of Capacitors, Diodes and Power Switches are decided by number of levels are generated in the output. For selecting the capacitors the formula is N-1. For selecting the Diodes the formula is (N-1)X(N-2). For selecting the Power Switches the formula 2X( N- 1).

      Figure 2.2 Waveform of five Level Diode Clamped MLI

   2. Capacitor Clamed Multi- Level Inverter

      Capacitor Clamped Multi- Level Inverter or Flying Capacitor Inverter consists mainly of Capacitors and Power switches, here there is an examples of five level Inverter is explained. This Converter consists of 8 Power Switches. Which means here also there is top 4 switches and bottom 4 four switches are present similarly the Dc voltage is separate top and bottom switches, but here the 1st and 8th switches are operated together, similarly 2nd and 7th Switches, 3rd and 6th Switches, 4th and 5th switches. These are connected by capacitors. This topology consists of DC bus incorporated with 4 capacitors C1 C2, C3, C4. Which produce VDC/ 4 Voltage in each capacitor.

      The figure 2.3 shows the Five Level Capacitor Clamped Multi Level Inverter. The operation is when the +vdc output is produced then the upper switches S1-S4 are operated, -Vdc is Produced then the Lower Switches S5-S8 are operated.

      Figure 2.3 Capacitor Clamped 5 Level MLI

      The figure 2.4 shows the waveform of Five Level Capacitor Clamped The total harmonics distortion of Five level CCMI and the output voltage of Five level CCMI consist of more harmonics distortion which will effect on the efficiency of inverter, whereas harmonic distortion in diode clamped multilevel inverter is very less.

      Figure 2.4 Waveform of five Level Diode Clamped MLI

   3. H- Bridge Multi Level Inverter

      The proposed switching technologies of inverter have five modes of operation. The power electronic switches S1 and S4 are used to provide positive voltages, which are called positive switches. Similarly the switches S2 and S3 are used to provide negative voltages, which are called negative switches. In first mode the switch S1 only goes to ON state and it provides Vs/2 as expected voltage. In second mode the positive switches S1 and S4 goes to ON state to provide Vs as expected voltage. In third mode the negative switch S2 goes to ON state and it provides -Vs/2 as expected voltage. In fourth mode the negative switch S2 and S3 are ON and provides Vs as expected voltage. In fifth mode all the switches are goes to OFF condition and hence it provides 0 as expected voltage. The Figure 2.5 and 2.6 shows the Cascade H- Bridge MLI and H- Bridge Waveform respectively.

      Figure 2.5 Cascade H Bridge MLI

      Figure 2.6 Waveform of Cascade H Bridge MLI

3. PROPOSED METHOD

   • In the proposed topology there are three boost factors Vdc, 2Vdc, 3vdc, -Vdc, -2Vdc, -3vdc. Which produce the seven level output. For each boost factors switches are operated at different pulse width, delay time etc.

   • Compared to other topology the number of switches are reduced and the switching stress are reduced, economically controlled, protection circuit also reduced. In proposed topology the number switches are reduced so that the voltage stress are high in switches, diode, capacitor. The boost factor will reduce the voltage stress by fast operation of switch.

   • This project we can able to extend the number of output voltage level by horizontal and vertical connections of capacitor. But one of the minor problem is number devices are added additionally in the circuit, it is not causes the major issues.

   1. Block diagram

      Figure 3.1 Block Diagram

      The Figure 3.1 Shows the block diagram of the entire unit. The following hardware are used in the project. DC voltage source, Switched capacitor, Cascade H- Bridge, Load or Microgrid

      The software required to simulate the entire unit MATLAB simulation tool.

   2. Circuit Diagram

      In front end Switched capacitor is used in this circuit we used two capacitors and four switches, at the back end H- Bridge is cascaded in this the Inductor Load is used.

      Figure 3.2 Circuit Diagram

      Figure 3.2 Shows the Circuit Diagram of Switched Capacitor and Cascade H- Bridge Inverter. IF available may also can connect to the micro grid also, instead of three H- Bridge circuit there is only one H- Bridge circuit is used and it consists of four switches. The boosting factor can be carried out by the switched capacitor.

   3. Switch Operation Table

   In this there are 3 boost factors and seven level of output voltage with inclusion of zero voltage. In the first mode boost factor operates, the switches are S4, H1, H4 are turned ON, hence the VDC output is produced.

   Table 3.1 Switch Operation Table

   OUTPUT VOLTAGE LEVEL	SWITCHES OPERATED
   VDC	S4	H1	H4	–
   2VDC	S1	H1	H4	–
   3VDC	S1	S2	H1	H4
   -VDC	H2	H3	–	–
   -2VDC	S1	H2	H3	–
   -3VDC	S1	S2	H2	H3

   The Table 3.1 a shows the current flow table of VDC, In the second mode boost factor operates, the switches are S1, H1, H4 are turned ON, hence the 2VDC output is produced. In the third mode boost factor operates the switches are S1, S2, H1, H4 are turned ON, hence the 3VDC output is produced, In the fourth mode boost factor operates, the switches are H2, H3 are turned ON, hence the -VDC output is produced. In the fifth mode boost factor operates, the switches are S1, H2, H3 are turned ON, hence the -2VDC output is produced. In the sixth mode boost factor operates the switches are S1,S2, H2, H3 are turned ON, hence the – 3VDC output is produced. The Table 4.1 shows the Switch operation Table.

4. SIMULATION RESULTS

   Figure 4.1 Shows the MATLAB Simulation model of Switched capacitor and cascade H- Bridge Multilevel Inverter, In this the Simulation and Output voltage, current, FFT Harmonics Percentage, capacitor C1 and C2 voltage are measured.

   Figure 4.1 MATLAB Simulation

   Figure 4.2 Load Output voltage

   The Figure 4.2 shows the Load Output voltage, with the waveform we can gather that with minimum component can able to produce the seven level output voltage for different application.

   Figure 4.3 Load Output Current

   Figure 4.3 shows the output load current, due to inductor load the output current differes from the output voltage, which means the if there is sudden drop in voltage, the inductor will slow down the current and gives gradual decreasing.

   Figure 4.4 THD output

   The Figure 4.4 shows the THD (Total Harmonics Distortion) the FFT harmonics wave infers that there is an 21.44% harmonics is present in the output voltage, thats due to some DC components present in the circuit.

   Figure 4.5 Capacitor C1 and C2 voltage

   The Figure 4.5 shows the Capacitor C1 and C2 Voltage, from the capacitor waveform the C1 capacitor deals with the positive cycle of the output voltage, the C2 capacitor deals with Negative cycle of the output voltage.

5. CONCLUSION

Thus with the help of the proposed inverter able to produce the seven stage of output voltage with less number of components. The inverter employees and achieves operation of the AC load with symmetric or asymmetric DC input. Highly cost economic, reduce the utilization of more number of power switches, no need to use the costlier protection circuits and also the number of protection circuit also reduced, by using the topology, compared to other topology the THD is reduced by the topology 21.44%, with the Seven stage output we can able to use for different kind of applications with low, medium, high power levels. Normally in Capacitor Clamped Multi- Level inverter needs more number of capacitors but the proposed topology consists of only two capacitors are used, with that C1 and C2 capacitors can ale to manage the both postive and negative cycle.

REFERENCE

1. Elyas Zamiri, Naser Vosoughi, Seyed Hossein Hosseini, Member, IEEE, Reza Barzegarkhoo and Mehran Sabahi A New Cascade Switched Capacitor Multi-Level Inverter Improved series and Parallel Conversion with Less number of Component.Member, IEEE,

2. J. Rodriguez, Jih-Sheng Lai and Fang Zheng Peng, "Multilevel inverters: a survey of topologies, controls, and applications," in IEEE Transactions on Industrial Electronics, vol. 49, no. 4, pp. 724-738, Aug. 2002.

3. Jih-Sheng Lai and Fang Zheng Peng, "Multilevel converters-a new breedof power converters," in IEEE Transactions on Industry Applications, vol. 32, no. 3, pp. 509-517, May-June 1996

4. Tapas Roy, Member, IEEE, and Pradip Kumar Sadhu A Step up Multilevel Inverter Topology using Novel Switched Capacitor Converters with Reduced Component, Member, IEEE

5. W. Peng, Q. Ni, X. Qiu and Y. Ye Seven-Level Inverter with Self- Balanced Switched-Capacitor and Its Cascaded Extension. in IEEE Transactions on Power Electronics. doi: 10.1109/TPEL.2019.29047.

6. Z. Li, P. Wang, Y. Li and F. Gao A Novel Single-Phase Five-Level Inverter With Coupled Inductors in IEEE Trans. Power Electron., vol. 27, no. 6, pp. 2716-2725, June 2012.