Three Phase Bridgeless Interleaved Active Power Factor Correction Converter

Three Phase Bridgeless Interleaved Active Power Factor Correction Converter

Three Phase Bridgeless Interleaved Active Power Factor Correction Converter

1 1

Tamilnadu, India

tkarthick2111@gmail.com1

Dr. V. Kamaraj3

Professor,

Department of Electricals & Electronics SSN College of Engineering, Kalavakkam Tamilnadu, India

kamarajv@ssn.edu.in2

Abstract- In this paper, a new three-phase acdc bridgeless interleaved power factor correction topology is proposed for battery charging applications. The topology provides improved power factor and efficiency in comparison to conventional bridge rectifier topology, and leads to a decrease in charger size, charging time and hence, is cost effective. A detailed circuit operation for this topology is presented. Simulation results are included for a boost converter converting AC input voltage 230 V to 750 V DC output. Simulation results show an improved power factor and reduced THD, when compared to conventional topology. Power factor in proposed BLIL PFC is improved by 2.19% and THD is reduced by 26.25%.

Keywords: Bridgeless Interleaved, THD, Power Factor, Displacment factor, Distortion factor, MatLab.

1. INTRODUCTION

   A Universal battery charger is supplied using an external power supply. The battery charger module as shown in fig.1 consists of AC and DC filters in line and load side respectively, an AC-DC Power Factor Correction (PFC) Boost converter is used for power factor correction which is followed by a DC-DC converter. A controller is used to control the charger set up. The AC-DC PFC boost converter is an important part in charger module. This AC-DC has to be selected carefully. For this a three-phase Bridgeless Interleaved (BLIL) PFC boost converter is proposed which will reduce the THD and increases the power factor.

   Fig.1. Block diagram of a universal battery charger

2. PROPOSED THREE-PHASE BLIL BOOST TOPOLOGY

   The Three-phase BLIL PFC converter shown in Fig. 2 is proposed to overcome the problems in conventional converters. The proposed three-phase BLIL PFC Converter,consists of six MOSFETs, six diodes,six inductors

   and a capacitor parallel to load. A detailed converter operation a steady- state analysis is given in the following section

   Fig.2. Proposed Three-Phase BLIL PFC Converter

3. CIRCUIT OPERATION AND STEADY STATE RIPPLE ANALYSIS

   To analyze the circuit operation, the input line cycle has been separated into the positive and negative half cycles. Operation for each of the half-line cycles are explained in Sections 3.1 and 3.2 that follow.

   1. POSITIVE HALF CYCLE OPERATION

      Referring to Fig. 2, during the positive half cycle, when Phase A and Phase B are conducting, Q1/Q2 turn on and current flows through L1 and Q1 and continues through Q2 (and partially its body diode) and then L2, returning to the line while storing energy in L1 and L2. When Q1/Q2 turn off, energy stored in L1 and L2 is released as current flows through D1, through the load and returns through the body diode of Q2 back to the input mains. With interleaving, the same mode happens for Q4/Q5, but with a 180 phase delay. The operation for this mode is Q4/Q5 on, storing energy in L4/L5 through the path L4-Q4-Q5-L5 back to the input. When Q4/Q5 turn off, en ergy is released through D4 to the load and returning through the body diode of Q5 back to the input mains.

      During the positive half cycle, when Phase B and Phase C are conducting, Q2/Q3 turn on and current flows through L2

      and Q2 and continues through Q3 (and partially its body diode)

      (5)

      and then L3, returning to the line while storing energy in L2 and L3. When Q2/Q3 turn off, energy stored in L2 and L3 is released as current flows through D2, through the load and returns through the body diode of Q3 back to the input mains. With interleaving, the same mode happens for Q5/Q6, but with a 180 phase delay. The operation for this mode is Q5/Q6 on, storing energy in L5/L6 through the path L5-Q5-Q6-L6 back to the input. When Q5/Q6 turn off, energy is released through D5 to the load and returning through the body diode of Q6 back to the input mains. During the positive half cycle, when Phase C and Phase A are conducting, Q3/Q1 turn on and current flows through L3 and Q3 and continues through Q1 (and partially its body diode) and then L1, returning to the line while storing energy in L3 and L1. When Q3/Q1 turn off, energy stored in L3 and L1 is released as current flows through D3, through the load and returns through the body diode of Q1 back to the input mains. With interleaving, the same mode happens for Q6/Q4, but with a 180 phase delay. The operation for this mode is Q6/Q4 on, storing energy in L6/L4 through the path L6- Q6-Q4-L4 back to the input. When Q6/Q4 turn off, energy is released through D6 to the load and returning through the body diode of Q4 back to the input mains.

      At this interval the change in capacitor voltage is given by

      (6)

      (7)

      (8)

      From Equation 8

      (9)

   2. NEGATIVE HALF CYCLE OPERATION

      Negative half cycle operation is similar to that of the positive half cycle operation but the current flow direction will be in the opposite direction to that of the positive half cycle.

      Where

      Ts=

      (10)

4. FINDING VALUES OF L AND C

   Designing the values of L and C is very important. In the proposed BLIL PFC Converter the values of L and C are designed as follows.

   Let us consider the instant when Phase A and Phase B are conducting. During this interval the voltage equation is given as

   (1)

   (2)

   Assuming matched inductors, L1, L2, L4 and L5, the input ripple current is the sum of currents in L1/L2 and L4/L5

   (3)

   R=output resistance

   Equation 5 and 10 gives the value of L and C respectively.

5. SIMULATION RESULTS

   1. CONVENTIONAL BOOST CONVERTER TOPOLOGY

      From Equation 3

      (4)

      Fig.3. MATLAB Implementation of Conventional Boost Converter Topology

      Design parameters:

      Switching Frequency : 25 KHz Input Voltage : 230 V

      Output Voltage : 753 V

      Duty Ratio : 0.67 Inductor : 131mH

      Resistor : 200

      Capacitor : 760µ F

      Magnitude of Voltage (V) and Current (A)

      Fig.4 and Fig.5 shows supply voltage and supply current and THD plot waveform of a Three-phase Conventional PFC respectively for duty ratio 67%

      Fig.4 Supply Voltage and Supply Current waveforms

      Fig.5 THD plot

      Power Factor= Kd * Kp Kd = cos, Kp= 1/

      = Phase difference between input voltage and current

      THD = Total Harmonic Distortion in input current Kd= Displacement Factor

      Kp= Distortion Factor

      Fig.6. MATLAB Implementation of Bridgeless Interleaved Boost Converter Topology

      Design parameters:

      Switching Frequency : 25 KHz Input Voltage : 230 V

      Output Voltage : 757 V

      Duty Ratio : 0.67/0.33 L1,L2,L3,L4,L5,L6 : 66.7 mH

      Capacitor C : 975 µ F

      Resistor R : 200

      R1,R2,R3,R,R5,R6 : 25m

      Fig.7 and Fig.8 shows supply voltage and supply current, THD plot and output voltage waveform of a Three-phase BLIL PFC respectively for duty ratio 67%

      Fig.7 Supply Voltage and Supply Current waveforms

      0.0017sec

      0

      15.3

      Cos

      Kd

      0.9645

      THD

      32.27%

      Kp 0.9510

      Fig.8 THD plot

      PowerFacto

      r Kd

      * Kp

      0.9172

   2. BRIDGELESS INTERLEAVED BOOST CONVERTER TOPOLOGY

      www.ijert.org 94

      0

      0.0022sec 24.3 Cos 09408

      Kd Cos 0.9408 THD 6.02%

      0

      0.0025sec 22.5 Cos Kd 0.9238 THD 18.63%

      Kp 0.9830

      Kp 0.9982

      PowerFactor

      Kd * Kp 0.9080

      PowerFactor

      Kp * Kd 0.9391

      Design parameters:

      Switching Frequency : 25 KHz Input Voltage : 230 V

      Output Voltage : 757 V

      Duty Ratio : 0.33 L1,L2,L3,L4,L5,L6 : 66.7mH

      Capacitor C : 975 µ F

      Resistor R : 200

      R1,R2,R3,R,R5,R6 : 25m

      Fig.9 and Fig.10 shows supply voltage and supply current and THD plot waveform of a Three-phase BLIL PFC respectively for duty ratio 33%

      Fig.9 Supply Voltage and Supply Current waveforms

      Fig.10 THD plot

6. COMPARISON OF THD AND POWER FACTOR

   Since, it is three-phase we have considered duty ratio as 67%. It is observed that the THD is reduced and the Power Factor is improved in proposed three-phase BLIL topology compared to three-phase conventional topology

   TOPOLOGY	THD (%)	POWER FACTOR
   Three-phase conventional (D=0.67)	32.27	0.9172
   Three-phase BLIL (D=0.67)	6.02	0.9391
   Three-phase BLIL (D=0.33)	18.36	0.9080

   Table1. Comparison of THD and power factor

   • Reduction in THD

     =32.27-6.02=26.25%

   • Improvement in Power Factor

   =0.9391-0.9172=0.0219

   =2.19%

7. CONCLUSION

   Thus from the above simulation results the following two were inferred. Duty ratio of 67% is best suited for three- phase converter topology. THD is reduced and Power Factor is improved in proposed three-phase BLIL PFC converter compared to Conventional topology.

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