Transistor Implementation of D Flip-Flop Using Reversible Logic Circuit

Transistor Implementation of D Flip-Flop Using Reversible Logic Circuit

Prashik Lokhande

Department of Electronics & Communication Engg.

K. J. Somaiya College of Engg. Mumbai, India

Jyoti Varavadekar

Department of Electronics & Communication Engg.

1. J. Somaiya College of Engg. Mumbai, India

   AbstractReversible logic circuit is receiving attention of researchers for low power design. Flip Flop is the basic element for the sequential circuits, most of the part of the IC is built from sequential circuit, and hence it is needed to design low power flip-flop. The work is done on designing a reversible D flip flop from a reversible Fredkin gate using GDI technique in 0.180um TSMC process, which can be used for low power design, and fault preventing circuit.

   Keyword Reversible D flip-flop; GDI

   1. INTRODUCTION

      As the complexity of the circuit grows power dissipation becomes an important factor. A part of energy is dissipated during non-ideal switching of transistor. Landauer showed that amount of energy dissipated when a bit is lost is given by KTlog2n where K is the Boltzmanns constant (1.3807X10-23 JK-1) and T is the temperature. For example, in room temperature (300 K), KT ln2 is approximately 2.8×10-21 J /transistor, which is not negligible for incoming multi-billion gate circuits. Bennet proposed that power not to be dissipated if circuit is implemented using reversible gates [1.] This solution promises the arbitrary small fraction of signal energy to be dissipated. Hence reversible logic circuit is getting attention of the researchers in many emerging fields such as nanotechnology, optical computing, and low power CMOS design. Section II gives the overview of reversible logic circuits, section III presents the circuit for d flip flop using reversible Fredkin gate, section IV presents transistor implementation of reversible D flip flop. Comparison with conventional flip-flop and conclusions are discussed in section V.

   2. CONCEPT OF REVERSIBLE LOGIC CIRCUITS

      1. Reversible Logic Function: A function is reversible if it satisfies following two criterions;

         1. Number of inputs equal to the number of outputs ii.Every output vector has a unique pre image

            If Iv (I1, I2, I3……In) is the input vector and Ov (O1, O2, O3

            …Ok) is the output vector then Iv = Ov.

      2. Reversible Logic Gate: A reversible logic gate is (n x k) device where n is the number of input bits and k is the number of output bits with one to one mapping i.e. n = k

         Fig.1 (a) NOT Gate (b) truth table of NOT gate

         In conventional circuits NOT gate is the only reversible gate, as from output its input can be determined. While, AND OR and XOR gates are irreversible, as we cant determine input to gate from their output.

      3. Quantum Cost: Every reversible gate has a cost associated with it known as quantum cost. Quantum cost of a reversible gate is the number of elementary operations required to implement its functionality, hence quantum cost defines the complexity of the circuit. Fig.1 shows a 1×1 simple NOT gate. All the reversible gates can be optimized by the NOT gate. If V is the root of NOT gate and V+ is its Hermitian, then the quantum cost of the gate is calculated by counting the number or of V and V+ in the gate.

         The quantum gates has the following properties

         V * V = NOT (1)

         V * V+ = V+ * V = I (2)

         V+ * V+ = NOT (3)

      4. Garbage output: This is the most important and prominent feature of reversible gate. The output of the gate which is not is used as the input to another gate is called garbage output.

         A reversible gate is realized by three basic components:

         Fig.2 Components of reversible circuit (a) dont care line (b) control line (c)

         target line

         The input on the dont care line is passed to output without change. Input at control line controls output on target line, if input to control line is 0 the input to target line will be passed as it is to its output and if input to control line is1 the inverse of the input line is passed to its output. There have been many reversible gates synthesized [2, 3, 4], of which CNOT or Toffoli gate are used mostly to synthesize the reversible circuits. Any reversible circuit can be implemented using CNOT and TOFFOLI gate; hence these gates are called universal reversible gates.

      5. NOT Gate: It is 1×1 reversible gate with zero quantum cost. The inputs get inverted at output, and hence we can determine the input to the gate, so it is the reversible gate present in conventional circuits.

         Fig.3 NOT Gate

      6. Feynman/CNOT gate: It is 2×2 reversible gate with quantum cost of 1. The black dot in the circuit shown in fig

      3.3 (b) is called control point. If A = 1, then inverse of B will be the output. As the NOT operation on B is controlled through control point by input A, the gate is called Controlled NOT.

      Fig.4 (a) CNOT Gate and (b) its Quantum realization

   3. Design of reversible D flip-flop To implement a flip flop we have equation,

      Q+ =D.CLK + Q.C L K (4)

      In literature Fredkin gate is a reversible gate whose output satisfies this equation. To make this gate to act like D-flip flop it is needed to have feedback. B is the data input; the output Q is the output of flip flop, which is feedback to input C as shown in figure 1.

      Figure.5 (a) Fredkin gate (b) D-flip flop using Fredkin gate

   4. TRANSISTOR IMPLEMENTATION OF REVERSIBLE D FLIP-FLOP

1. Gate diffusion input (GDI):

   The GDI method uses a simple cell called GDI cell, shown in figure 6, it has three inputs the GDI cell contains three inputs: G (common gate input of both the nMOS and the pMOS), P (input to the source/drain of the pMOS), and N (input to the source/drain of the nMOS). Table I shows how a simple change to the input configuration of the simple GDI cell corresponds to a large variety of Boolean functions. Most of these functions are complex (612 transistors) in Static CMOS, as well as in standard PTL implementations, but very simple (only two transistors per function) in the GDI design method comparison shown in table II.

   Fig.6 basic GDI cell

   Similar to most of the PTL solutions, the GDI gates suffer from threshold voltage drops at their outputs. These drops affect the circuit operation in two ways: (1) performance degradation due to reduced current drive; (2) increase in the circuits area, as cascaded regenerative inverters are required. But still the GDI technique is efficient than CMOS as it has low power dissipation [6, 7, 8].

   TABLE I. BOOLEAN FUNCTION SYNTHESIS THROUGH INPUT CONFIGURATION OF GDI

   N	P	G	Out	Function
   0	B	A	B	F1
   B	1	A	+	F2
   1	B	A	A+B	OR
   B	0	A	AB	AND
   C	B	A	B+AC	MUX
   0	1	A		NOT

   Style	AND	OR	XOR
   GDI	2	2	4
   CMOS	6	6	12
   TG	6	6	8
   N-PG	4	4	6

   TABLE II. COMPARISON OF NUMBER OF TRANSISTORS REQUIRED TO DESIGN GATES

2. Transistor implementation of reversible D flip-flop

   Fig.7 Implementation of Reversible D flip flop through GDI

   From fig 5 implantation of the reversible D flip-flop is carried out through GDI shown in fig7. In this circuit the output R is same as clock input, so transistors forming output R are removed to reduce transistor count, which results in circuit shown in fig 8.

   Fig.8 D flip-flop using Reversible logic circuit

3. Comparison of Reversible and Conventional D flip-flop The conventional circuit for D flip-flop implemented through GDI is given in paper [9].

Fig.9 conventional GDI flip-flip

TABLE III. COMPARISON BETWEEN CONVENTIONAL AND REVERSIBLE FLIP FLOP

CONCLUSION

In this paper transistor implementation of D flip-flop using Reversible logic circuit is carried out. The analysis is shown in table III, indicating that about 40% less power is dissipated than the conventional circuit. This circuit can be used to design registers and memories for ultra low power design.

REFERENCES

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4. Madhusmita Mahapatro, Sisira Kanta Panda, Design of Arithmetic Circuits Using Reversible Logic Gates and Power Dissipation Calculation, 2010 International Symposium on Electronic System Design, 2010 IEEE.

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6. Morgenshtein, Idan Shwartz and Alexander Fish, Gate Diffusion Input (GDI) Logic in Standard CMOS Nanoscale Process, 26-th Convention of Electrical and Electronics Engineers in Israel. 2010 IEEE.

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   1. Wagner, IEEE transactions on very large scale integration (VLSI) systems, VOL. 10, NO. 5, OCTOBER 2002.

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9. Arkadiy Morgenshtein, Alexander Fish and Israel A. Wagner, An efficient implementation of D-flip-flop using the GDI technique, ISCAS 2004 IEEE.