VTMOS Circuits Realization through DTMOS Circuits

VTMOS Circuits Realization through DTMOS Circuits

VTMOS Circuits Realization through DTMOS Circuits

Dr.K. Ragini,1 Dr. M. Satyam,2 and Dr. B.C. Jinaga,3

1

G. Narayanamma Institute of Technology & Science ,

Department of Electronics and Communication Engineering, Hyderabad, India2 International Institute of Information Technology, Hyderabad, India3 School of Information Technology, Jawaharlal Nehru Technology University, Hyderabad, India

Abstract : Variable Threshold MOS (VTMOS) circuits have been proposed as a circuit style for low power VLSI systems. They are suitable for sub threshold digital circuit operations. Basically, the principal of sub threshold logic is operating MOSFET in sub threshold region and using the leakage current in that region for switching action, thereby drastically decreasing power. The present paper studies the VTMOS through Dynamic Threshold MOS (DTMOS) by connecting a bias voltage between gate and substrate. The new technique improves circuit performance over DTMOS and consumes less power. Simulations done using 65nm CMOS technology shows that the proposed technique improves inverters logic levels, saving power over the DTMOS scheme at 0.2v supply voltage and upto 2Mhz operating frequency.

Introduction: In the past, the conventional sub threshold CMOS logic was proposed, which uses the leakage current for switching operation [1, 2, 3]. In DTMOS, the threshold voltage is altered, dynamically to suit the operating state of circuit. A high threshold voltage in the standby mode gives low leakage current, while a low threshold voltage allows higher current drives in active mode of operation. DTMOS can be achieved by connecting the gate and body together [4]. In variable threshold MOSFET, the gate is connected to substrate through a biasing voltage. This bias voltage causes large variation of threshold voltage, with gate voltage than in DTMOS.

In VTMOS circuits ,the ratio (r = Ion / Ioff) increases with bias voltage, thus providing a good variation between high and low currents. This higher Ion/Ioff results in good discrimination between VOH and VOL logic levels and reduces overall power dissipation [5]. In view of this, the performance of VTMOS has been studied and its implication on the performance of circuits using this operation is investigated.

This article is organised as follows – In section 1, the typical schematic structures of CMOS, DTMOS and VTMOSFETS are given. Section 2 has description of the various experiments (through simulation) carried out on current-voltage characteristics of N and PMOSFETS with VTMOS configuration. In section 3, estimation of Ids as a function of Vgs and VAN is made . The behavior of VTMOS inverter has been described in section 4 from the point of power dissipation, delay characteristics, power delay product and noise – margin. Section 5 shows the results and analysis where it has been found that VTMOS Inverters consume considerably low power with marginal change in the delay characteristics. Section 6 concludes the article.

Section 1:

Structure of MOS, DTMOS and VTMOS configuration.

Typical schematic structures of CMOS, DTMOS and VTMOSFETS are given in Fig 1 (a), 1 (b) and 1 (c). In conventional NMOS circuit, Fig. 1(a), the substrate is normally connected to ground or lowest potential in the circuit. In PMOS circuits, the substrate is connected to supply voltage or the highest potential in the circuit. In DTMOS, Fig 1 (b) the substrate is always kept at gate potential. So when gate potential is varied, substrate potential also varies [6, 7]. Variation in substrate potential results in variation in threshold voltage and hence the transfer characteristics of DTMOS are different from that of conventional CMOS devices [8].

VTMOS is nothing but an extension of DTMOS in the sense that the substrate voltage differs always by a constant voltage from the gate voltage as shown in Fig 1(c).

Section 2

I-V characteristics of MOS devices

To evaluate the behaviour of NMOS devices under VTMOS operating conditions, the I-V characteristics are measured and are given in Fig (2) and Fig (3) [9]. It may be observed from Fig (2) and Fig (3) that general current levels (Ion and Ioff) get reduced with increase in bias voltage when NMOS gate is positively biased with respect to substrate and in the PMOS case, when gate is negatively biased with respect to substrate.

The ratio (r = Ion/Ioff) has been calculated for bias voltages VAN in the range of 0 to 0.2V, and is shown in Table (1).DTMOS is nothing but a special case of VTMOS with VAN =0V. It may be seen that the ratio increases with VAN, thus providing a good variation between high and low currents. In order to examine the effect of substrate bias on I-V output characteristics of VTMOS, Ids verses Vds for different substrate bias voltages, Keeping Vgs = 0.2v have been measured and are given in Fig (3).

It may be seen that the variation in Ids with Vds, becomes less as VAN is made positive (deep sub threshold region). The characteristics may become flat, indicating that the output resistance becomes high. Thus the drain current is less sensitive to variations in drain voltages, which is a welcome feature for application of device in circuits.

An attempt has been made to estimate the Ids – Vgs curve for typical VAN for NMOS device and is described in section 3.

Section 3

Estimation of Ids as a function of Vgs and VAN for NMOS [10].

In the sub threshold region, the drain current, Ids is exponentially related to gate volatage, Vgs and is shown in equation (1).

V V

Vds

gs th V

Ids = Io exp 1 exp

– (1)

Vtm

W

tm

where Io =

L

eff Cox Vtm2

Where Vtm Thermal voltage, KT/q (=25 mv at 25oC)

eff effective mobility (0.06m2/vs) W Transistor width (200N)

L Transistor length (70N)

Cox

= ox

/ tox

or

=

=

tox

tox oxide thickness = 1.7 nm

o 8.854 x 10-12F/M

r Relative permittivity (3.9) Vth Threshold voltage

The Threshold voltage equation is

Vth = Vto + Vbs – 2

Vto Threshold voltage at zero bias (0.22)

= Bulk threshold parameter (0.43)

0.4 + V

Ndep

ln

tm

ni

where Vtm thermal voltage = 0.025 Ndep channel doping concentration

2.6 x 1018

ni Intrinsic carrier concentration

1.02 x 1010 cm-3

0.8993

In order to estimate the Ids-Vgs characteristics for NMOS, the following steps are to be considered.

Step1 : For VAN = 0.2v, Vgs is varied from 0 to 0.2v, the threshold voltage is calculated from equation (2) for the given parameters.

Step 2. The calculated threshold voltage value is substituted in current Ids equation (1) and corresponding Ids value is obtained.

Step 3. The Ids – Vgs values are tabulated and compared with simulated values, in Table (2).

In this case, an attempt has been made to estimate Ids – Vgs characteristics using the above equations with BSIM level – 54 MOS model parameters. The calculated values are given in Table 2(a).

Since these characteristics are calculated with only limited values of parameters, the characteristics have been simulated using all the default parameters (reference : as given in HSPICE manual).

The Ids – Vgs curve for 0.2v is given in Table 2(a)(manual)and 2(b)(simulated). From these tables it may be seen that the estimated values are diferent from those values obtained through direct simulation. Therefore one may use expressions to obtain the trends, rather than to obtain actual values. Further investigations use only the simulated values.

Section 4 VTMOS Inverter

The VTMOS Inverter as shown in Fig (4) consists of a PMOS and NMOSFETS, connected in series. The substrate of PMOS is connected to gate through VAP, which bias the gate negative with respect to substrate. The substrate of NMOS is connected, to the gate through VAN which bias the gate positive with respect to substrate. This ensures that both transistors work in the low current region. The transistors for VTMOS are chosen from the 65 nm technology. The threshold voltage for these devices are 0.22v for NMOS and-0.22v for PMOS. The width of NMOS (WN) and PMOS (WP) is chosen as 200 nm and 400 nm respectively. The supply voltage is taken as 0.2v which is below the threshold of both the devices.

For different values of VAN starting from O to 0.2v, and corresponding VAP from 0 to – 0.2v, the performance of the inverter – logic levels, power dissipation, frequency response and propagation delay have been obtained, through simulation. When the bias voltage is increased beyond supply voltage, the logic levels are affected. Hence there is a limitation for bias voltage and it should be always below supply voltage.

In the first instance, the transfer characteristics of VTMOS with VAN varying from 0 to 0.2v and VAP varying from 0 to -0.2v have been obtained for VDS = 0.2v. In order to compare these characteristics with CMOS , transfer characteristics of these cases are also obtained in Fig (5). The corresponding logic levels and noise margins are shown in Table (3) and Table(4).

The other important characteristics, of the inverter, i.e. power dissipation, frequency response, propagation delay, have been obtained and reported [9].

In this case the input is taken in the form of square wave varying from 0 to 0.2 v with a rise and fall time of 25 ns. The frequency of square wave is varied over a range of 1 Khz to 2 Mhz.

Section 5

Results and Analysis

This section is sub divided as follows: In section 5.1, the VTC characteristics and logic levels of all inverters are compared. The transient characteristics of inverters are discussed in section 5.2 and effect of frequency on the static and dynamic characteristics are discussed in section 5.3.

Section 5.1

Voltage transfer characteristics / DC Transfer characteristics

The voltage transfer characteristics plots the output voltage as a function of input voltage. For DC analysis the Voltage Transfer characteristics (VTC) of CMOS and VTMOS with various VAN's are compared in Fig (5). It may be seen that the VTC characteristics of all circuits are similar.

The logic levels in CMOS and VTMOS with various VAN's ranging from 0 to 0.2v are given in Table (3). It may be seen that, as the bias voltage VAN is increased, the output logic low VOL tends to go down with VAN for a Vgs of 0.2v. The logic high output VOH also go up marginally with VAN. These variations are within tolerable limits for VTMOS and provide good logic swing.

Noise margin : A measure of sensitivity of a gate to noise is given by the noise margin's NML and NMH, which indicate the range of O and I respectively.

To find the noise- margin , the input and output logic levels are required. Both VOH and VOL are obtained from characteristics, and is shown in Table(3).The input logic levels, both VIH and VIL are the points at which the VTC characteristics has slope of -1.To find these points ,the curve for the derivative of VTC is to be obtained, and the two points at which the value is -1 is to be found and that gives VIL and VIH logic levels.

NML = VIL – VOL NMH = VOH – VIH

A large noise margin is always desirable. The noise margin of CMOS and VTMOS with various VAN are calculated and are given in Table (4).

The noise margin increases as one go from CMOS to VTMOS (0.2v).

Section 5.2

Transient (Dynamic Characteristics of Inverter)

The variation of Propagation delay, power dissipation and power delay product for different devices ( CMOS and VTMOS with various VANS) are given in Table (5) for a frequency of 100KHZ and at Vdd = 0.2V. From Table (5) the following conclusion are made.

1. Propagation delay. The propagation delay associated with the inverter has been calculated through the values of TPLH and TPHL obtained through simulation, for various values of VAN, and given in table (5). It was been found that the propagation delay increases as one increase VAN.

2. Power dissipation : The power consumed by the inverter for a square wave of 0.2v amplitude with varying VAN at a frequency of 100 Khz has been measured further and given in Table (5). It has been found that the power dissipation decreases considerably with increase in VAN.

3. Power delay product : From Table (5) it may be seen that, while the power dissipation decreases with increase in VAN, the delay has been found to be increased. In order to get an idea of the merit of operating the inverter in sub threshold region, the power delay product has been computed and given in the same table (5). It may be seen that , the PDP decreases with increase in VAN . Thus the VTMOS appear to have an edge over the other configuration from the point of power and delay.

   Section 5.3

   Effect of frequency on the static and dynamic characteristics.

   The static and dynamic characteristics mentioned above have been measured for various types of Inverters at the frequency range of 1 Khz to 2 Mhz.

   In order to get an idea of the effect of frequency on the dynamic characteristics, they are measured at different frequencies ranging from 1Khz to 2Mhz.

   It has been found that the general nature of variation of power dissipation and propagation delays are maintained as those reported at 100 Khz. However, the power dissipation increases with frequency and the variation of power dissipation with frequency for CMOS and VTMOS(0 to 0.2v) is shown in Fig(7). Propagation delay and logic levels remain almost constant with frequency. The power dissipation in VTMOS increases faster than in the case of CMOS inverter and there is no visible advantage of operating the inverter in VTMOS mode beyond 2Mhz.

   Section 5.4 :

   Estimation of power consumption

   The overall average power consumption in conventional CMOS devices can be expressed as the sum of 3 main components.

   1. The dynamic (switching) power consumption.

   2. The short – circuit power consumption.

   3. The leakage power consumption or static power consumption.

The dynamic power is a result of power consumed in charging and discharging load capacitance in the circuit. Short circuit power arises when a conducting path between supply voltage and ground is formed. Static power is the power dissipated while the device is turned off.

2

2

The Table (6) shows the three components of power for CMOS and VTMOS with various VAN. For a device with Cload =10fF and frequency = 100 Khz, static power dissipation is dominant power at 100 khz, when compared to dynamic and short circuit power. Both static and short-circuit power components are obtained through simulation and dynamic power is calculated by the equation Pdyn = Cload VDD fclk.

Conclusions : From the observation made and analysis done, the following conclusions have been arrived at. With a view to reduce the power dissipation of CMOS and DTMOS circuits, the gate is biased positive with respect to substrate for NMOS and biased negative with respect to substrate for PMOS. Currents

flowing through the channel is further reduced compared to CMOS and DTMOS devices resulting in further reduction in power dissipation.

Further the leakage current which flows through out the operation is also reduced. In view of this, these circuits which we call as VMOS have been visualized simulated and the performance has been measured. The measurement include transfer characteristics of VTMOS devices with drain voltage 0.2V less than the threshold voltage of FET for different values of VAN for both P and N MOSFETS. Through this transfer characteristics, the leakage or static power is estimated. This is followed by simulation of the inverter with different VAN values. The power consumed and the corresponding delay for different VAN's at different frequencies have been measured. The power delay product with VAN at specific frequency has been estimated. It has been found that the power dissipation in general, decreases with increase in VAN upto input frequency of 2Mhz and it is lower than the power consumed by CMOS and DTMOS Inverters. However the PDP improves only upto 500 khz. It may be possible to further increase the frequency response by appropriately designing the transistors to suit the requirements.

Figure captions:

Fig. 1 : Structures of CMOS DTMOS and VTMOS configuration.

Fig. 2 (a) : Ids-Vgs characteristics of VTMOS with VAN varying from 0 to 0.2v.

Fig. 2 (b) : Ids – Vgs characteristics of VTMOS with VAN varying from 0 to 0.2V (zoomed versions) to get Ioff of VTMOS.

Fig. 3 : Ids – Vds characteristics of VTMOS with VAN varying from 0 to 0.2V.

Fig. 4 : VTMOS inverter

Fig. 5 : Voltage transfer characteristics of CMOS and VTMOS

Inverter with VAN varying from 0 to 0.2v.

Fig. 6 : Frequency versus power dissipation for VTMOS

Inverter with VAN varying from 0 to 0.2v.

Figure 1a – CMOS Structure

Figure 1b – DTMOS Structure

Figure 1b – DTMOS Structure

Figure 1b – DTMOS Structure

Figure 1c – VTMOS Structure

Figure 2a -Ids – Vgs Characteristics of VTMOS VAN Varying from 0(top) to 0.2V(Bottom)

Figure (2b)- Ids-Vgs Curves for VTNMOS-VAN Varying From 0(Top) TO 0.2V(Bottom) (Zomed Version)

Fig 3- Ids-Vds Curves For VTNMOS-VAN Varying From 0(Top) TO 0.2V(Bottom)

Figure 4 VTMOS Inverter

VAP

VAN

Figure 5 Voltage Transfer characteristics of CMOS and VTMOS (VAN varying from 0 to 0.2 V)

1 2 3 4 5 6

1.20E-09

1.00E-09

8.00E-10

6.00E-10

4.00E-10

2.00E-10

0.00E+00

DTMOS

VTMOS(VAN- 0.05V)

VTMOS(VAN-0.1V)

VTMOS(VAN- 0.15V)

VTMOS(VAN-0.2V)

Frequency

n

o i t

a

p i

s

s i

d r e

w o P

Power dissipation

Power dissipation

n

o i t

a

p i

s

s i

d r e

w o P

Frequency

DTMOS

VTMOS(VAN- 0.05V)

VTMOS(VAN-0.1V)

VTMOS(VAN- 0.15V)

VTMOS(VAN-0.2V)

1.20E-09

1.00E-09

8.00E-10

6.00E-10

4.00E-10

2.00E-10

0.00E+00

1 2 3 4 5 6

Table Captions:

Table 1 VAN versus Ion / Ioff ratio.

Table 2 Ids – Vgs curve for VAN = 0.2V and Vds = 0.2V

Table 3 Logic levels for CMOS and VTMOS with VAN varying from 0 to 0.2 volts.

Table 4 Noise margins are compared for CMOS and VTMOS with VAN varying from 0 to 0.2 volts.

Table 5 Variation of propagation delay, power dissipation and power delay product for CMOS and VTMOS with VAN varying from 0 to 0.2v.

Table 6 Components of Power and total estimated power is compared with average power dissipation for CMOS and VTMOS varying from 0 to 0.2v.

TABLES

Table:1 Table – 2 (a) Table – 2 (b)

Manual Simulation

Table-3 Table – 4

Table -5

Cload = 10ff freq = 100 khz PULSE (0 0.2 0 0.025u 0.025U 5U 10.05U)

Table 6 – Components of power dissipation

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